AD5398 Analog Devices, AD5398 Datasheet - Page 4

• Manufacturer Part Number: AD5398
• Description: 120 mA, Current Sinking, 10-Bit, I2C D/A Converter
• Manufacturer: Analog Devices

Specifications of AD5398

• Resolution (bits): 10bit
• Dac Update Rate: 31kSPS
• Dac Settling Time: 250µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: I2C/Ser 2-wire,Ser

AD5398
AC SPECIFICATIONS
V
Table 2.
Parameter
Output Current Settling Time
Slew Rate
Major Code Change Glitch Impulse
Digital Feedthrough
1
2
3
TIMING SPECIFICATIONS
V
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
SCL
1
2
3
4
5
6
7
8
9
10
11
falling edge.
Temperature range is as follows: B Version: –40°C to +85°C.
Guaranteed by design and characterization; not production tested.
See the Terminology section.
Guaranteed by design and characterization; not production tested.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
C
b
DD
DD
2
b
is the total capacitance of one bus line in pF. t
= 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance R
= 2.7 V to 5.5 V. All specifications T
SDA
SCL
1
Limit at T
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
300
20 + 0.1 C
400
3
t
9
B Version
CONDITION
START
MIN
b
3
t
4
, T
MAX
t
3
R
MIN
and t
Min
to T
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns max
ns min
pF max
t
F
10
are measured between 0.3 V
t
MAX
6
Figure 2. 2-Wire Serial Interface Timing Diagram
, unless otherwise noted.
Typ
250
0.3
0.15
0.06
B Version
Description
SCL clock frequency
SCL cycle time
t
t
t
t
t
t
t
t
t
May be CMOS driven
t
t
Capacitive load for each bus line
HIGH
LOW
HD, STA
SU, DAT
HD, DAT
SU, STA
SU, STO
BUF
R,
F
F
t
2
, fall time of SDA when receiving
, fall time of both SCL and SDA when transmitting
Rev. B | Page 4 of 16
rise time of both SCL and SDA when receiving
, bus free time between a stop condition and a start condition
L
, SCL low time
, SCL high time
= 25 Ω connected to V
, setup time for repeated start
, stop condition setup time
, start/repeated start condition hold time
, data setup time
, data hold time
1, 2
Max
t
11
t
DD
5
and 0.7 V
IH MIN
DD.
Unit
μs
mA/μs
nA-s
nA-s
of the SCL signal) in order to bridge the undefined region of SCL’s
CONDITION
REPEATED
START
DD
t
7
, unless otherwise noted.
t
Test Conditions/Comments
V
¼ scale to ¾ scale change (0x100 to 0x300)
1 LSB change around major carry
4
DD
= 5 V, R
L
t
= 25 Ω, L
1
L
= 680 μH
CONDITION
STOP
t
8