AD5382 Analog Devices, AD5382 Datasheet
AD5382
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AD5382 Summary of contents
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... DAC REG7 REG7 14 m REG7 14 c REG7 ×4 LDAC Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113© 2004–2010 Analog Devices, Inc. All rights reserved. AD5382 REFGND REFOUT/REFIN SIGNAL_GND (×4) 1.25V/2.5V REFERENCE 14 DAC 0 VOUT0 DAC 1 ...
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... DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces ..... Serial Interface ..................................................................... 28 Parallel Interface ......................................................................... 30 Microprocessor Interfacing ....................................................... 31 Application Information ................................................................ 33 Power Supply Decoupling ......................................................... 33 Typical Configuration Circuit .................................................. 33 Monitor Function ....................................................................... 34 Toggle Mode Function ............................................................... 34 Thermal Monitor Function ....................................................... 35 AD5382 in a MEMS-Based Optical Switch ............................ 35 Optical Attenuators .................................................................... 36 Outline Dimensions ....................................................................... 37 Ordering Guide .......................................................................... 37 Rev Page ...
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... GENERAL DESCRIPTION The AD5382 is a complete, single-supply, 32-channel, 14-bit DAC available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operation. The AD5382 includes an internal software-selectable 1. ppm/°C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common ...
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... MΩ min Typically 100 MΩ ±1 μA max Typically ± min/max AVDD/2 Enabled via CR10 in the AD5382 control register; CR12 selects the reference voltage 2.495/2.505 V min/max At ambient; CR12 = 1; optimized for 2.5 V operation 1.22/1.28 V min/max 1.25 V reference selected; CR12 = 0 ±10 ppm/°C max Temperature Range: +25° ...
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... AD5382-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. 2 Accuracy guaranteed from VOUT = AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded accuracy specifications. 1 AD5382-5 Unit Test Conditions/Comments ...
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... MΩ min Typically 100 MΩ ±10 μA max Typically ± min/max AVDD/2 Enabled via CR10 in the AD5382 control register, CR12 selects the reference voltage 1.245/1.255 V min/max At ambient; CR12 = 0; optimized for 1.25 V operation 2.47/2.53 V min/max 2.5 V reference selected; CR12 = 1 ±10 ppm/°C max Temperature Range: +25° ...
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... Accuracy guaranteed from VOUT = AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded accuracy specifications CHARACTERISTICS AVDD 3.6 V; DVDD = 2 5.5 V; AGND = DGND ...
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... AD5382 TIMING CHARACTERISTICS SPI-, QSPI-, MICROWIRE-, OR DSP-COMPATIBLE SERIAL INTERFACE DVDD = 2 5.5 V; AVDD = 3.6 V; AGND = DGND = 0 V; all specifications T unless otherwise noted. Table Parameter Limit MIN ...
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... DB0 DB23 NOP CONDITION DB23 SELECTED REGISTER DATA CLOCKED OUT DB0 DB23 INPUT WORD FOR DAC DB23 INPUT WORD FOR DAC N Rev Page AD5382 DB0 DB0 DB0 DB0 ...
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... AD5382 SERIAL INTERFACE DVDD = 2 5.5 V; AVDD = 3.6 V; AGND = DGND = 0 V; all specifications T unless otherwise noted. Table Parameter Limit MIN MAX F 400 SCL 100 300 300 ...
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... BUSY rising edge to LDAC falling edge ns min LDAC falling edge to DAC output response time μs typ DAC output settling time ns min CLR pulse width low μsmax CLR pulse activation time ) and timed from a voltage level of 1 Rev Page AD5382 ...
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... AD5382 REG0, REG1, A4...A0 DB13...DB0 BUSY LDAC VOUT1 LDAC VOUT2 CLR VOUT LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY Figure 7. Parallel Interface Timing Diagram Rev ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev Page AD5382 ...
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... Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are internally shorted and should be decoupled with a 0.1 μF ceramic capacitor and a 10 μF tantalum capacitor. Operating range for the AD5382 5.5 V; operating range for the AD5382 3.6 V. DGND Ground for All Digital Circuitry ...
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... Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of SCLK. In parallel interface mode, this pin acts as the data register select when writing data to the AD5382’s data registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the LDAC is used to switch the output between the data contained in the A and B data registers ...
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... AD5382 Mnemonic Function PD Power Down (Level Sensitive, Active High used to place the device in to low power mode where the device consumes 2 μA AIDD and 20 μA DIDD. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured ...
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... Offset error is a measurement of the difference between VOUT (actual) and VOUT (ideal) in the linear region of the transfer function, expressed in mV. Offset error is measured on the AD5382-5 with Code 32 loaded into the DAC register, and on the AD5382-3 with Code 64. Gain Error Gain error is specified in the linear region of the output range between VOUT and VOUT = AVDD – ...
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... Rev Page AVDD = DVDD = 1.25V REF T = 25° 4096 8192 12288 INPUT CODE Figure 12. Typical AD5382-3 INL Plot AVDD = DVDD = 1.25V REF T = 25°C A 14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 5nV 100 150 ...
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... Rev Page Figure 18. Power-Up Transient AVDD = 5.5V REFIN = 2. 25°C A – INL ERROR DISTRIBUTION (LSB) Figure 19. INL Error Distribution PD AVDD = DVDD = 2.5V REF VOUT T = 25°C A EXITS HARDWARE PD TO MIDSCALE Figure 20. Exiting Hardware Power-Down AD5382 ...
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... REFOUT = 1.25V 100 0 100 1k 10k FREQUENCY (Hz) Figure 23 REFOUT Noise Spectral Density V = 2.5V REF T = 25°C A – Figure 24. AD5382-3 Output Amplifier Source and Sink Capability 2.456 AVDD = 2.5V REF T = 25°C 2.455 A 2.454 2.453 2.452 2.451 2.450 2.449 1.50 1.75 2.00 100k Rev Page ...
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... All channels are double buffered, allowing synchronous updating of all channels using the LDAC pin. block diagram of a single channel on the AD5382. The digital input transfer function for each DAC can be represented – [(m + 2)/2 × ...
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... ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) The AD5382 contains a number of special function registers (SFRs), as outlined in Table 15. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bits A4 to A0. Table 15. SFR Register Functions (REG1 = 0, REG0 = 0) R ...
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... CR13 = 0. Amplifier output is 100 kΩ to ground. CR12: REF Select. This bit selects the operating internal reference for the AD5382. CR12 = 1: Internal reference is 2.5 V (AD5382-5 default), the recommended operating reference for AD5382-5. CR12 = 0: Internal reference is 1.25 V (AD5382-3 default), the recommended operating reference for AD5382-3. ...
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... AD5382 Table 18. AD5382 Channel Monitor Decoding REG1 REG0 ...
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... BUSY AND LDAC FUNCTIONS BUSY is a digital CMOS output that indicates the status of the AD5382. The value of x2, the internal data loaded to the DAC data register, is calculated each time the user writes new data to the corresponding x1 register. During the calculation of x2, the BUSY output goes low ...
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... A/B Figure 3 and Figure 5 show timing diagrams for a serial write to the AD5382 in standalone and daisy-chain modes. The 24-bit 2 C-compatible. The data-word format for the serial interface is shown in Table 19. A /B. When toggle mode is enabled, this pin selects whether the data write is to the register. With toggle disabled, this bit should be set select the A data register ...
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... SDO. Figure 30 shows the readback sequence. For example, to read back the m register of Channel 0 on the AD5382, the following sequence should be implemented. First, write 0x404XXX to the AD5382 input register. This configures the AD5382 for read mode with the m register of Channel 0 selected. Data Bits DB13 to DB0 are don’ ...
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... SDA and SCL facilitate communication between the AD5382 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagrams that incorporate three different modes of operation. In selecting the I ...
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... SDA REG1 REG0 MSB MOST SIGNIFICANT DATA BYTE AD1 AD0 R ACK BY MSB AD538x LSB MSB ACK BY AD538x 2 Figure 31. 4-Byte AD5382 Write Operation AD1 AD0 R ACK BY MSB AD538x LSB MSB ACK BY AD538x DATA FOR CHANNEL "N" ACK BY ...
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... The REG0 and REG1 pins determine the destination register of the data being written to the AD5382. See Table 11. Pins Each of the 40 DAC channels can be addressed individually. Pins DB13 to DB0 The AD5382 accepts a straight 14-bit parallel word on DB13 to DB0, where DB13 is the MSB and DB0 is the LSB. AD1 AD0 R/W ...
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... The lower address lines from the processor are connected to A0–A4 on the AD5382. The upper address lines are decoded to provide LDAC signal for the AD5382. The fast interface timing of the AD5382 allows direct interface to a wide variety of microcontrollers and DSPs, as shown in ...
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... LSB first, the transmit routine must take this into account. 8XC51 1 ADDITIONAL PINS OMITTED FOR CLARITY. 1 AD5382 AD5382 to ADSP-2101/ADSP-2103 SER/PAR Figure 38 shows a serial interface between the AD5382 and the RESET ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should SDO be set up to operate in SPORT transmit alternate framing mode. DIN SCLK The ADSP-2101/ADSP-2103 SPORT is programmed through ...
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... The printed circuit board on which the AD5382 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5382 system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only, a star ground point established as close to the device as possible ...
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... Table 16 Figure toggle mode implementation. Each of the 32 DAC channels on the AD5382 contains an A and B data register. Note that the B registers can be loaded only when toggle mode is enabled. The sequence of events when configuring the AD5382 for toggle mode is as follows: 1 ...
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... DACs that offer high channel density with 14-bit monotonic behavior. The 32-channel, 14-bit AD5382 DAC satisfies these requirements. In the circuit in Figure 43, the outputs of the AD5382 are amplified to achieve an output range 200 V, which is used to control actuators that determine the position of MEMS mirrors in an optical switch ...
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... PORTS OPTICAL SWITCH PHOTODIODES 11 ATTENUATOR 12 ATTENUATOR 1n–1 ATTENUATOR 1n ATTENUATOR N:1 MULTIPLEXER AD5382, 32-CHANNEL, 14-BIT DAC CONTROLLER 16-BIT ADC Figure 44. OADM Using the AD5382 as Part of an Optical Attenuator Rev Page DWDM OUT AWG FIBRE TIA/LOG AMP (AD8304/AD8305) ADG731 (32:1 MUX) AD7671 (0V TO 5V, 1MSPS) ...
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... VIEW A 0.50 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026BED Figure 45. 100-Lead Low Profile Quad Flat package [LQFP] (ST-100-1) Dimensions shown in millimeters Output AVDD Range Channels Rev Page AD5382 76 75 12.00 REF 51 50 0.27 0.22 0.17 Linearity Package Package Error Description Option ± ...
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... AD5382 NOTES Rev Page ...
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... NOTES Rev Page AD5382 ...
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... AD5382 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). © 2004–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03733–0–4/10(B) Rev Page ...