AD5381 Analog Devices, AD5381 Datasheet - Page 32

• Manufacturer Part Number: AD5381
• Description: 40-Channel 12-Bit 3 V/5 V Single-Supply Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5381

• Resolution (bits): 12bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par,Ser,SPI

AD5381
AD5381 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the Clock Polarity Bit = 0. This is done
by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 microcontroller user manual.
In this example I/O, Port RA1 is being used to pulse SYNC
and enable the serial port of the AD5381. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive read/write operations
may be needed depending on the mode. Figure 36 shows the
connection diagram.
AD5381 to 8051
The AD5381 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode 0.
In this mode, serial data enters and exits through RxD, and a
shift clock is output on TxD. Figure 37 shows how the 8051 is
connected to the AD5381. Because the AD5381 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5381
requires its data to be MSB first. Since the 8051 outputs the
LSB first, the transmit routine must take this into account.
PIC16C6X/7X
SDO/RC5
SCK/RC3
SDI/RC4
Figure 36. AD5381-to-PIC16C6x/7x Interface
RA1
DVDD
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I
AD5381
2
C
Rev. B | Page 32 of 40
AD5381 to ADSP-2101/ADSP-2103
Figure 38 shows a serial interface between the AD5381 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and configured as follows: internal
clock operation, active low framing, and 16-bit word length.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled.
ADSP-2101/
ADSP-2103
8XC51
Figure 38. AD5381-to-ADSP-2101/ADSP-2103 Interface
P1.1
SCK
RxD
RFS
TxD
TFS
DR
DT
Figure 37. AD5381-to-8051 Interface
DVDD
DVDD
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I
AD5381
AD5381
2
2
C
C