AD5390 Analog Devices, AD5390 Datasheet
AD5390
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AD5390 Summary of contents
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... FEATURES AD5390: 16-channel, 14-bit voltage output DAC AD5391: 16-channel, 12-bit voltage output DAC AD5392: 8-channel, 14-bit voltage output DAC Guaranteed monotonic INL ±1 LSB max (AD5391) ±3 LSB max (AD5390-5/AD5392-5) ±4 LSB max (AD5390-3/AD5392-3) On-chip 1.25 V/2 ppm/°C reference Temperature range: − ...
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... Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 AD5390-5/AD5391-5/AD5392-5 Specifications ..................... 4 AD5390-5/AD5391-5/AD5392-5 AC Characteristics............. 6 AD5390-3/AD5391-3/AD5392-3 Specifications ..................... 7 AD5390-3/AD5391-3/AD5392-3 AC Characteristics............. 9 Timing Characteristics ................................................................... 10 Serial SPI-, QSPI-, MICROWIRE-, and DSP-Compatible Interface ....................................................................................... Serial Interface ...................................................................... 12 Absolute Maximum Ratings .......................................................... 13 ESD Caution ...
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... AD5383BST-5 12 Bits 4 5.5 V AD5383BST-3 12 Bits 2 3.6 V The AD5390/AD5391/AD5392 contain a 3-wire serial interface with interface speeds in excess of 30 MHz that are compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards 2 and an I C-compatible interface supporting a 400 kHz data transfer rate. ...
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... AD5390/AD5391/AD5392 SPECIFICATIONS AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external. All specifications unless otherwise noted. Table 2. Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Offset Error Offset Error TC Gain Error 2 Gain Temperature Coefficient 2 DC Crosstalk ...
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... SINK SINK Outputs unloaded, boost off, 0.25 mA/channel typ Outputs unloaded, boost on, 0.325 mA/channel typ DGND Typically 200 nA Typically 3 μA AD5390/AD5391 with outputs unloaded boost off DD DD AD5392 with outputs unloaded boost off DD DD ...
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... AD5390/AD5391/AD5392 AD5390-5/AD5391-5/AD5392-5 AC CHARACTERISTICS 5.5 V; AGND = DGND = Table 3. Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time AD5390/AD5392 AD5391 2 Slew rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise (0 ...
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... AD5390-3/AD5391-3/AD5392-3 SPECIFICATIONS 5.5 V; AGND = DGND = 0 V; REFIN = 1.25 V external. All specifications unless otherwise noted. Table 4. Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Offset Error Offset Error TC Gain Error 2 Gain Temperature Coefficient DC Crosstalk REFERENCE INPUT/OUTPUT ...
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... V to 5.5 V, SDO only, sourcing 200 μ SINK SINK Outputs unloaded, boost off, 0.25 mA/channel typ Outputs unloaded, boost on, 0.325 mA/channel typ DGND AD5390/AD5391 with outputs unloaded boost off DD DD AD5392 with outputs unloaded boost off DD DD ...
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... AD5390-3/AD5391-3/AD5392-3 AC CHARACTERISTICS 5.5 V; AGND = DGND = Table 5. Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time AD5390/AD5392 AD5391 2 Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough OUTPUT NOISE (0 ...
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... BUSY rising edge to DAC output response time ns min BUSY rising edge to LDAC falling edge ns min LDAC falling edge to DAC output response time μs typ DAC output settling time, AD5390/AD5392 μs typ DAC output settling time, AD5391 ns min CLR pulse width low μs max ...
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... DB0 DB0 DB23' NOP CONDITION DB23 SELECTED REGISTER DATA CLOCKED OUT I 200µ (MIN (MAX) L 50pF I 200µA OH Rev Page AD5390/AD5391/AD5392 DB0 DB0 ...
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... AD5390/AD5391/AD5392 SERIAL INTERFACE 5.5 V; AGND = DGND = 0 V. All specifications Table Serial Interface 2 Parameter Limit MIN MAX F 400 SCL 100 300 300 11 0 300 ...
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... ESD CAUTION −0 0 −0 0 −0 −0 −0 +0.3 V −0 0 −40°C to +85°C −65°C to +150°C 150°C 22°C/W 38°C/W 230°C Rev Page AD5390/AD5391/AD5392 ...
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... NC VOUT VOUT VOUT AGND 2 35 VOUT 15 VOUT VOUT 14 VOUT VOUT CONNECT Figure 9. AD5390/AD5391 LQFP Pin Configuration CLR BUSY 46 RESET REF_GND REFOUT/REFIN SIGNAL_GND ...
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... The default for this pin is a reference input. MON_OUT Analog Output Pin. When the monitor function is enabled on the AD5390/AD5391, the MON_OUT acts as the output of a 16-to-1 channel multiplexer that can be programmed to multiplex any channel output to the MON_OUT pin. When the monitor function is enabled on the AD5392, the MON_OUT acts as the output of an 8-to-1 channel multiplexer that can be programmed to multiplex any channel output to the MON_OUT pin ...
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... AD5390/AD5391/AD5392 Mnemonic Function PD Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes 1 μA analog current and 20 μA digital current. In power-down mode, all internal analog circuitry is placed in low power mode; the analog output is configured as high impedance outputs or provides a 100 kΩ load to ground, depending on how the power-down mode is configured ...
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... Output Noise Spectral Density DD This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hz measured by loading all DACs to midscale and measuring noise at the output measured in nV/(Hz) bandwidth at 10 kHz. Rev Page AD5390/AD5391/AD5392 1 ...
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... INPUT CODE Figure 12. AD5390-3/AD5392-3 INL Plot –2 –1 0 INL ERROR DISTRIBUTION (LSB) Figure 13. AD5390/AD5392 INL Histogram Plot 1. 5. VREF = 2.5V 0. 25°C A 0.50 0.25 –0.25 –0.50 –0.75 –1.00 12288 16384 1. VREF = 1 ...
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... Rev Page AD5390/AD5391/AD5392 VREF = 2.5V 3/4 SCALE T = 25°C A MIDSCALE 1/4 SCALE ZERO SCALE –20 –10 –5 – CURRENT (mA) Figure 20 ...
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... AD5390/AD5391/AD5392 1.254 VREF = 1.25V 1.253 T = 25°C A 14ns/SAMPLE NUMBER 1.252 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 5nV-s 1.251 1.250 1.249 1.248 1.247 1.246 1.245 0 50 100 150 200 250 300 350 SAMPLE NUMBER Figure 23. AD539x-3 Glitch Impulse VREF = 2. 25° ...
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... 25°C A DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE Y AXIS = 5µV/DIV X AXIS = 100ms/DIV Figure 29. 0 Output Noise Plot AD5390/AD5391/AD5392 VREF = 1.25V T = 25° 3/4 SCALE 3 MIDSCALE ZERO SCALE –1 –40 –20 –10 –5 Figure 30. AD539x-3 Source and Sink Current Capability Rev ...
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... AD5390/AD5392 and 0xFFE on the AD5391). The LSB of the gain coefficient is zero DAC resolution ( for the AD5390/AD5392 and for the AD5391 the 12-bit and 14-bit offset coefficient (default is 0x2000 on the AD5390/AD5392 and 0x800 on the AD5391) ...
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... DATA DECODING AD5390/AD5392 The AD5390/AD5392 contain an internal 14-bit data bus. The input data is decoded depending on the data loaded to the REG1 and REG0 bits of the input serial register. This is shown in Table 10. Data from the serial input register is loaded into the addressed DAC input register, offset (c) register, or gain (m) register. The format data, and the offset (c) and gain (m) register contents are shown in Table 11 to Table 13 ...
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... INTERFACE The serial interface can be operated with a minimum of three wires in standalone mode or four wires in daisy-chain mode. Daisy-chaining allows many devices to be cascaded together to increase system channel count. The SPI/ I Table 18. AD5390 16-Channel, 14-Bit DAC Serial Input Register Configuration MSB ...
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... SCLK signal. If the SCLK idles high between the write and read operations of a readback, the first bit of data is clocked out on the falling edge of SYNC . 24 DB0 DB23 DB0 DB23 UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 32. Readback Operation Rev Page AD5390/AD5391/AD5392 48 DB0 NOP CONDITION DB0 ...
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... C pin to Logic 0, the device is connected to the slave device, that is, no clock is generated by the device. The AD5390/AD5391/AD5392 have a 7-bit slave address 1010 1 (AD1)(AD0). The five MSBs are hard-coded and the two LSBs are determined by the state of the AD1 and AD0 pins. The hardware configuration facility for the AD1 and AD0 pins allows four of these devices to be configured on the bus ...
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... SDA MOST SIGNIFICANT DATA BYTE DAC to be addressed and is also acknowledged by the DAC. Address Bits address all channels on the AD5390/ AD5391. Address Bits address all channels on the AD5392. Address Bit zero on the AD5392. Two bytes of data are then written to the DAC, as shown in A STOP condition follows ...
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... SDA low. The address byte is followed by the pointer byte; this addresses the specific channel in the DAC to be addressed and is also acknowledged by the DAC. Address Bits address all channels on the AD5390/AD5391. Address Bits address all channels SCL 1 0 ...
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... ACK BY LEAST SIGNIFICANT DATA BYTE CONVERTER CHANNEL 1 DATA LSB MSB ACK BY CONVERTER CHANNEL N DATA FOLLOWED BY STOP 2 Figure 36. 2-Byte Mode I C Write Operation Rev Page AD5390/AD5391/AD5392 ACK BY POINTER BYTE CONVERTER LSB ACK BY CONVERTER LSB ACK BY CONVERTER LSB ACK LEAST SIGNIFICANT DATA BYTE ...
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... CLR pin. The DAC outputs are loaded with the data in the CLR code register. The time taken to execute fully the SOFT CLR is 20 μs on the AD5390/AD5391 and 15 μs on the AD5392 indicated by the BUSY low time. Soft Power-Down REG1 = REG0 = 1000 DB13 to DB0 = Don’ ...
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... Table 23. AD5390/AD5392 Channel Monitor Decoding REG1 REG0 ...
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... AD5390/AD5391/AD5392 CONTROL REGISTER WRITE Table 25 shows the control register contents for the AD5390 and the AD5392. Table 26 provides bit descriptions. Note that REG1 = REG0 = 1100, and DB13 to DB0 contain the control register data. Table 25. AD5390/AD5392 Control Register Contents MSB ...
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... CR1 Group 1 Channel 8 to Channel 15 CR0 Group 0 Channel 0 to Channel 7 Logic 1 written to any bit enables a group of channels and Logic 0 disables a group. LDAC is used to toggle between the two registers. CR7 CR6 CR5 CR4 Rev Page AD5390/AD5391/AD5392 LSB CR3 CR2 CR1 CR0 ...
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... CLR register and sets the analog outputs accordingly. This function can be used in system calibration to load zero scale and full scale to all channels together. The execution time for a CLR is 20 μs on the AD5390/AD5391 and 15 μs on the AD5392. BUSY AND LDAC FUNCTIONS BUSY is a digital CMOS output indicating the status of the AD539x devices ...
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... SPORT control register and should be configured DIN as follows: internal clock operation, active low framing, and SCLK 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. SYNC Rev Page AD5390/AD5391/AD5392 DV DD AD539x 8xC51 RESET 2 SPI/I ...
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... AD539x control register. On the AD5390/AD5392, Control Register Bit CR12 lets the user choose the reference voltage; Bit CR10 is used to select the internal reference recommended to use the 2.5 V reference when and the 1 ...
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... Configuring the AD5390, for example, the user writes to the control register and sets CR3 = 1 and CR2 = 1, enabling the two groups of eight for toggle mode operation. The user must then load data to all 16 A registers and B registers ...
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... AD5390/AD5391/AD5392 12- and 14-bit resolution. Figure 45 shows a typical transmitter architecture, in which the AD539x DACs can be used in the following control circuits: I control, average power control BIAS (APC), peak power control (PPC), transmit gain control (TGC), and audio level control (ALC). DACs are also required for variable voltage attenuators, phase shifter control, and dc- setpoint control in the overall amplifier design ...
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... COPLANARITY VIEW A 0.65 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BCC Figure 49. 52-Lead Low Profile Quad Flat Package [LQFP] (ST-52) Dimensions shown in millimeters Rev Page AD5390/AD5391/AD5392 0.60 MAX PIN 1 INDICATOR 64 1 7.25 EXPOSED PAD 7.10 SQ (BOTTOM VIEW) 6. 0.25 MIN 7.50 REF FOR PROPER CONNECTION OF ...
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... AD5390BCP-5 −40°C to +85°C AD5390BCP-5-REEL −40°C to +85°C AD5390BCP-5-REEL7 −40°C to +85°C 1 AD5390BCPZ-5 −40°C to +85°C 1 AD5390BCPZ-5-REEL −40°C to +85°C 1 AD5390BCPZ-5-REEL7 −40°C to +85°C 1 AD5390BSTZ-3 −40°C to +85°C 1 AD5390BSTZ-5 −40°C to +85°C AD5391BCP-3 − ...