AD5391 Analog Devices, AD5391 Datasheet - Page 10

• Manufacturer Part Number: AD5391
• Description: 16-Channel 12-Bit 3V/5V Single-Supply Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5391

• Resolution (bits): 12bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser,SPI

AD5390/AD5391/AD5392
TIMING CHARACTERISTICS
SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE
DV
Table 6. 3-Wire Serial Interface
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
1
2
3
4
5
6
7
7
8
9
10
11
12
13
14
15
16
17
17
18
19
20
21
22
23
Guaranteed by design and characterization, not production tested.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
See Figure 2, Figure 3, Figure 4, and Figure 5.
Standalone mode only.
Daisy-chain mode only.
4
4
4
4
4
4
4
5
DD
= 2 V to 5.5 V; AV
2, 3
SYNC
LDAC
SCLK
SDO
DIN
Limit at T
33
13
13
13
13
33
10
50
5
4.5
30
670
20
20
100
0
100
8
6
20
12
20
5
8
20
DD
= 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications T
t
7
1
MIN
t
DB23
4
, T
MAX
t
INPUT WORD FOR DAC N
8
t
9
Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode)
UNDEFINED
t
3
CC
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
μs typ
μs typ
ns min
μs max
ns max
ns min
ns min
ns min
t
) and timed from a voltage level of 1.2 V.
1
t
2
Rev. C | Page 10 of 40
24
DB0
DB23
DB23
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24
Minimum SYNC low time
Minimum SYNC high time
Minimum SYNC high time in readback mode
Data setup time
Data hold time
24
BUSY pulse width low (single channel update)
24
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time, AD5390/AD5392
DAC output settling time, AD5391
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
th
th
th
t
20
SCLK falling edge to SYNC falling edge
SCLK falling edge to BUSY falling edge
SCLK falling edge to LDAC falling edge
INPUT WORD FOR DAC N+1
INPUT WORD FOR DAC N
MIN
to T
t
MAX
21
, unless otherwise noted.
48
DB0
DB0
t
t
23
22
t
13