AD5348 Analog Devices, AD5348 Datasheet - Page 5

• Manufacturer Part Number: AD5348
• Description: 2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 12-Bit D/A Converter
• Manufacturer: Analog Devices

Specifications of AD5348

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par

TIMING CHARACTERISTICS
Table 3. V
Parameter
Data Write Mode (Figure 3)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Data Readback Mode (Figure 4)
t
t
t
t
t
t
t
t
t
t
t
1
2
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Guaranteed by design and characterization, not production tested.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
See Figure 2.
GAIN, BUF
LDAC
LDAC
A0–A2
DATA,
DD
CLR
WR
CS
1
2
= 2.5 V to 5.5 V; all specifications T
Figure 3. Parallel Interface Write Timing Diagram
NOTES
1. SYNCHRONOUS LDAC UPDATE MODE
2. ASYNCHRONOUS LDAC UPDATE MODE
t
1
t
6
t
3
t
t
t
t
7
9
14
4
t
2
Limit at T
0
0
20
5
4.5
5
5
4.5
5
4.5
20
10
20
20
0
0
0
0
20
30
0
22
30
4
30
22
30
30
30
30
50
t
t
t
5
8
10
t
15
1, 2, 3
t
13
MIN
t
11
, T
t
MIN
12
MAX
to T
DD
MAX
) and timed from a voltage level of (V
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
Rev. 0 | Page 5 of 24
, unless otherwise noted
Condition/Comments
CS to WR setup time
CS to WR hold time
WR pulse width
Data, GAIN, BUF setup time
Data, GAIN, BUF hold time
Synchronous mode. WR falling to LDAC falling.
Synchronous mode. LDAC falling to WR rising.
Synchronous mode. WR rising to LDAC rising.
Asynchronous mode. LDAC rising to WR rising.
Asynchronous mode. WR rising to LDAC falling.
LDAC pulse width
CLR pulse width
Time between WR cycles
A0, A1, A2 setup time
A0, A1, A2 hold time
A0, A1, A2 to CS setup time
A0, A1, A2 to CS hold time
CS to falling edge of RD
RD pulse width; V
RD pulse width; V
CS to RD hold time
Data access time after falling edge of RD; V
Data access time after falling edge of RD V
Bus relinquish time after rising edge of RD
CS falling edge to data; V
CS falling edge to data; V
Time between RD cycles
Time from RD to WR
Time from WR to RD, V
Time from WR to RD, V
A0–A2
DATA
WR
CS
RD
Figure 4. Parallel Interface Read Timing Diagram
DD
DD
= 3.6 V to 5.5 V
= 2.5 V to 3.6 V
t
IL
16
+ V
t
DD
DD
t
26
18
t
IH
23
DD
DD
= 3.6 V to 5.5 V
= 2.5 V to 3.6 V
t
)/2.
21
= 3.6 V to 5.5 V
= 2.5 V to 3.6 V
t
AD5346/AD5347/AD5348
19
t
t
22
20
t
17
t
24
DD
DD
= 2.5 V to 3.6 V
= 3.6 V to 5.5 V
t
25