AD5583 Analog Devices, AD5583 Datasheet
AD5583
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AD5583 Summary of contents
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... Optical Network Control Loops Current Transmitter GENERAL DESCRIPTION The AD5582/AD5583 family of quad, 12-/10-bit, voltage output digital-to-analog converters is designed to operate from a single dual ±5 V supply. It offers the user ease of use in single- or dual-supply systems. Built using an advance BiCMOS process, this high performance DAC is dynamically stable, capable of high current drive, and in small form factor ...
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... AD5582 and 155 for AD5583 H Data = 555 for AD5582 H Code = Full Scale AD5582 AD5583 Data = 800 for AD5582 and H £ 200 for AD5583 OUT Data = 800 for AD5582 and H £ |–8 mV| 200 for AD5583 OUT £ ± OUT No Oscillation = 5 V ± ...
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... These parameters are guaranteed by design and not subject to production testing. 5 Dual-supply operation exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors. REFL SS 6 Short circuit output and supply currents are 24 mA and 25 mA, respectively. ...
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... These parameters are guaranteed by design and not subject to production testing. 5 Dual-supply operation exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors. REFL SS 6 Short circuit output and supply currents are 24 mA and 25 mA, respectively. ...
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... RDH t RDS CSD L t CSP t LDS t LDH = 2 ns (10 and timed from a voltage level of 1 –5– AD5582/AD5583 10 –40 C < T REFH REFL A Min Typ Max 20 130 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5582/AD5583 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... VOD 45 V SS2 46 V DD2 47 VOC 48 AGND2 –7– AD5582/AD5583 Data Bit 6 Data Bit 7 Digital Ground 2 Data Bit 8 Data Bit 9 Data Bit 10 Data Bit 11 Address Input 0 Address Input 1 Chip Select, Active Low Read/Write Mode Select Digital Ground 3 Negative Power Supply for Analog Switches ...
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... Data Bit 1 22 DGND1 Digital Ground 1 23 DB2 Data Bit 2 24 DB3 Data Bit 3 *AD5583 optimizes internal layout design to reduce die area so that all supply voltage pins are required to be connected externally. See Figure 5. AD5583 PIN CONFIGURATION AGND1 AGND2 1 48 VOB VOC 2 47 ...
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... WCS t = 35ns 35ns AS ADDRESS ADDRESS ADDRESS ONE TWO THREE t = 0ns LDS t = 35ns WDS DATA1 DATA2 DATA3 VALID VALID VALID –9– AD5582/AD5583 t = 0ns WH ADDRESS FOUR t = 0ns 0ns WDH DATA4 VALID = 0ns WH ADDRESS FOUR t = 0ns LDH t = 20ns LDW ...
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... AD5582/AD5583 CS R/W A0/ LDAC DATA IN RS Figure 2c. Data Write (Input and Output Registers) Timing CS R/W A0/A1 DATA OUT t = 20ns WCS t = 35ns 35ns 0ns = 0ns 35ns WDS t = 20ns RESET t = 130ns RCS 35ns = 0ns RDS RDH t = 35ns t = 0ns 100ns MAX CSD ...
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... DAC-C DAC-D –0.6 –0.8 –1.0 0 128 256 384 512 CODE (Decimal) TPC 3. AD5583 Integral Nonlinearity Error REV. A Typical Performance Characteristics–AD5582/AD5583 2560 3072 3584 4096 TPC 4. AD5583 Differential Nonlinearity Error 2560 3072 3584 4096 TPC 5. AD5582 INL, DNL, ZSE, and GE at Positive ...
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... AD5582/AD5583 1 0 REFH 0 REFL R 0 260 L 0.2 0 –0 790 L –0 390 L –0.6 RESISTIVE LOAD R IS BETWEEN L –0.8 V AND GND OUT –1.0 0 512 1024 1536 2048 CODE (Decimal) TPC 7. AD5582 INL at Various Resistive Loads 0 0 REFH 0 ...
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... REFL 100 120 140 TPC 17. AD5582 Referenced Input Resistance 10k TPC 18. AD5582 Supply Current vs. Clock Frequency –13– AD5582/AD5583 REFH REFL 0 512 1024 1536 2048 2560 3072 CODE (Decimal) TPC 16. AD5582 Reference Current ...
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... AD5582/AD5583 –100 –90 –80 –70 –60 –50 –40 –30 –20 – 100 1k FREQUENCY (Hz) TPC 19. AD5582 PSRR vs. Frequency V 200mV/DIV OUT V 200mV/DIV 5 s/DIV REF TPC 20. Small Signal Response Operating at Near Rail (See Test Circuit 1) L 100 90 V 2V/DIV OUT s/DIV DATA 5V/DIV TPC 21 ...
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... DAC C L Test Circuit 1 THEORY OF OPERATION The AD5582/AD5583 are quad, voltage output, 12-/10-bit parallel input DACs in compact TSSOP-48 packages. Each DAC is a voltage switching, high impedance ( kW), R-2R ladder configuration with segmentation to optimize die area and precision. Figure 3 shows a simplified R-2R structure without the segmentation. The 2R resistances are switched ...
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... R1 and R2. These resistors are matched within ± 0.025% for the AD5582 and 0.1% for the AD5583, which is equivalent to less than 1 LSB mis- match. Figure 4 shows a simple configuration. Common reference or references can be applied to all four chan- nels, but each reference pin should be decoupled with a 0 ...
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... R3 in theory can be made small to achieve the current needed within the U4 output current driving capability. In this circuit, the AD8510 can deliver ± both directions and the voltage compliance approaches ± REV. A Table I. AD5582/AD5583 Logic Table INPUT DAC RS REGISTER REGISTER ...
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... The differential gain control interface allows the use of either differential or single-ended positive or negative control voltages, where the common-mode range is –1 +2.0 V. The AD5582/AD5583 is ideally suited to provide the differential input range within the common-mode range accomplish this, place V then all 4096 V levels of the AD5582 will fall within the gain control range of the AD603 ...
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... Thin Shrink Small Outline Package [TSSOP PIN 1 0.15 0.05 REV. A OUTLINE DIMENSIONS (RV-48) Dimensions shown in millimeters 12.60 12.50 12.40 25 6.20 6.10 6.00 8.10 BSC 24 1.20 MAX 8 0.5 0 0.27 SEATING 0.20 BSC 0.17 PLANE 0.09 COMPLIANT TO JEDEC STANDARDS MO-153ED –19– AD5582/AD5583 0.75 0.60 0.45 ...
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... AD5582/AD5583 Revision History Location 8/03—Data Sheet changed from REV REV. A. Change to Figure Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Changes to Figures 2a –20– Page REV. A ...