AD5308 Analog Devices, AD5308 Datasheet - Page 8

• Manufacturer Part Number: AD5308
• Description: 2.5 V to 5.5 V Octal Voltage Output 8-Bit DACs in 16-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD5308

• Resolution (bits): 8bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5308/AD5318/AD5328
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
LDAC
SYNC
V
V
V
V
V
V
V
V
V
V
V
GND
DIN
SCLK
DD
OUT
OUT
OUT
OUT
REF
REF
OUT
OUT
OUT
OUT
ABCD
EFGH
A
B
C
D
E
F
G
H
Description
This active low control input transfers the contents of the input registers to their respective DAC registers. Pulsing
this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simul-
taneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges
of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an
interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Reference Input Pin for DACs A, B, C, and D. It can be configured as a buffered, unbuffered, or V
DACs, depending on the state of the BUF and V
mode and from 1 V to V
Reference Input Pin for DACs E, F, G, and H. It can be configured as a buffered, unbuffered, or V
DACs, depending on the state of the BUF and V
mode and from 1 V to V
Buffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input. The DIN input buffer is powered down after each write cycle.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
DD
DD
in buffered mode.
in buffered mode.
V
REF
V
V
V
V
ABCD
LDAC
SYNC
OUT
OUT
OUT
OUT
V
DD
A
B
C
D
Figure 3. Pin Configuration
1
2
3
4
5
6
7
8
Rev. F | Page 8 of 28
(Not to Scale)
AD5308/
AD5318/
AD5328
TOP VIEW
DD
DD
control bits. It has an input range from 0.25 V to V
control bits. It has an input range from 0.25 V to V
16
15
14
13
12
11
10
9
SCLK
DIN
GND
V
V
V
V
V
OUT
OUT
OUT
OUT
REF
EFGH
H
G
F
E
DD
DD
input to the four
input to the four
DD
DD
in unbuffered
in unbuffered