AD9744 Analog Devices, AD9744 Datasheet
AD9744
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AD9744 Summary of contents
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... DAC solution. The digital inputs support 3 V CMOS logic families. PRODUCT HIGHLIGHTS 1. The AD9744 is the 14-bit member of the pin compatible TxDAC family, which offers excellent INL and DNL performance. 2. Data input supports twos complement or straight binary data coding. ...
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... DAC Transfer Function ............................................................. 14 Analog Outputs........................................................................... 14 Digital Inputs .............................................................................. 15 Clock Input.................................................................................. 15 DAC Timing................................................................................ 16 Power Dissipation....................................................................... 16 Applying the AD9744 ................................................................ 17 Differential Coupling Using a Transformer............................ 17 Differential Coupling Using an Op Amp ................................ 17 Single-Ended Unbuffered Voltage Output .............................. 18 Single-Ended, Buffered Voltage Output Configuration........ 18 Power and Grounding Considerations, Power Supply Rejection ...................................................................................... 18 Evaluation Board ...
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... V 7 kΩ 0.5 MHz 0 ppm of FSR/°C ±50 ppm of FSR/°C ±100 ppm of FSR/°C ±50 ppm/°C 3.3 3.6 V 3.3 3.6 V 3.3 3 135 145 mW 145 FSR/V +0. FSR/V +85 °C = 100 MSPS and MHz. CLOCK OUT AD9744 ...
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... AD9744 DYNAMIC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) CLOCK 1 Output Settling Time (t ) (to 0.1%) ST Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) 1 Output Fall Time (10% to 90%) ...
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... OUTFS Min 2.1 −10 −10 2.0 1.5 1.5 0 0.75 0 LPW 0.1% Figure 2. Timing Diagram Rev Page Min Typ Max Typ Max 3 0 0.9 +10 + 1.5 2.25 1.5 0.1% AD9744 Unit dBc dBc dBc dBc Unit V V µA µ ...
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... AD9744 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD DVDD CLKVDD ACOM ACOM DCOM AVDD AVDD DVDD CLOCK, SLEEP Digital Inputs, MODE IOUTA, IOUTB REFIO, REFLO, FS ADJ CLK+, CLK−, CMODE Junction Temperature Storage Temperature Lead Temperature (10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; ...
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... Clock Common. Rev Page DB7 ADJ PIN 1 INDICATOR DB6 2 23 REFIO DVDD 3 22 ACOM AD9744 DB5 4 21 IOUTA DB4 5 20 IOUTB TOP VIEW 19 ACOM DB3 6 (Not to Scale) DB2 7 18 AVDD DB1 8 17 AVDD CONNECT Figure 4. 32-Lead LFCSP AD9744 ...
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... It is measured as the difference between the rms amplitude of a carrier tone to the peak spuri- ous signal in the region of a removed tone. . For offset and gain 3.3V REFLO AVDD ACOM 150pF AD9744 PMOS CURRENT SOURCE ARRAY IOUTA SEGMENTED SWITCHES LSB IOUTB SWITCHES FOR DB13– ...
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... OUT Figure 10. SFDR vs 210 MSPS OUT 20mA 10mA (MHz) OUT Figure 11. SFDR vs. f and MSPS and 0 dBFS OUT OUTFS AD9744 5mA 25 ...
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... AD9744 65MSPS 210MSPS (LFCSP 210MSPS 65 165MSPS –25 –20 –15 –10 A (dBFS) OUT Figure 12. Single-Tone SFDR vs. A OUT 95 90 65MSPS 85 125MSPS (LFCSP 165MSPS 55 125MSPS 210MSPS (LFCSP –25 –20 –15 –10 A (dBFS) OUT Figure 13. Single-Tone SFDR vs. A ...
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... Figure 22. Two-Carrier UMTS Spectrum 122.88 MSPS (ACLR = 64 dB) LFCSP Package CLOCK RES BW = 30kHz VBW = 300kHz ATTEN = 8dB AVG = 50 SPAN 18MHz LOWER UPPER REF BW dBc dBm dBc 3.840MHz –74.62 –84.12 –75.04 Figure 23. Single-Carrier UMTS Spectrum 61.44 MSPS (ACLR = 74 dB) LFCSP Package CLOCK AD9744 36 dBm –84.54 ...
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... AD9744 V REFIO I REF 0.1µF R SET 2kΩ 3.3V CLOCK 3.3V REFLO AVDD 150pF +1.2V REF AD9744 REFIO PMOS FS ADJ CURRENT SOURCE ARRAY DVDD LSB SEGMENTED SWITCHES DCOM FOR DB13–DB5 SWITCHES CLOCK LATCHES SLEEP DIGITAL DATA INPUTS (DB13–DB0) Figure 24. Simplified Block Diagram (SOIC/TSSOP Packages) Rev ...
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... I SET REF V REFIO Figure 27. External Reference Configuration REFERENCE CONTROL AMPLIFIER The AD9744 contains a control amplifier that is used to regulate the full-scale output current, I configured as a V-I converter, as shown in Figure 26, so that its current output determined by the ratio of the V REF an external resistor the segmented current sources with the proper scale factor to set stated in Equation 3 ...
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... IOUTA and IOUTB is limited to ±0.5 V. (4) The distortion and noise performance of the AD9744 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier ...
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... IOUTA and IOUTB does not exceed 0.5 V. DIGITAL INPUTS The AD9744 digital section consists of 14 input bit channels and a clock input. The 14-bit parallel data inputs follow stan- dard positive binary coding, where DB13 is the most significant bit (MSB) and DB0 is the least significant bit (LSB) ...
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... SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω AVDD. This digital input also contains an active pull- down circuit that ensures that the AD9744 remains enabled if this input is left disconnected. The AD9744 takes less than power down and approximately 5 µs to power back up. POWER DISSIPATION ...
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... CLKVDD CLOCK APPLYING THE AD9744 Output Configurations The following sections illustrate some typical output configura- tions for the AD9744. Unless otherwise noted assumed that I is set to a nominal 20 mA. For applications requiring the OUTFS optimum dynamic performance, a differential output configu- ration is suggested ...
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... In this case, AVDD, which is the positive analog supply for both the AD9744 and the op amp, is also used to level-shift the differen- tial output of the AD9744 to midsupply (that is, AVDD/2). The AD8041 is a suitable op amp for this application. ...
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... OUT IN Proper grounding and decoupling should be a primary objec- tive in any high speed, high resolution system. The AD9744 features separate analog and digital supplies and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible ...
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... The digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to operate the AD9744 with either the internal or external reference or to exercise the power-down feature. DB13X ...
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... WHT R2 10kΩ JP2 MODE REF TP3 C1 C2 WHT 0.1µF 0.1µF C11 R1 0.1µF AVDD 2kΩ IY Figure 42. SOIC Evaluation Board—Output Signal Conditioning Rev Page AD9744 JP10 R11 IOUTA 50Ω C13 OPT JP8 OPT ...
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... AD9744 Figure 43. SOIC Evaluation Board—Primary Side Figure 44. SOIC Evaluation Board—Secondary Side Rev Page ...
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... Figure 45. SOIC Evaluation Board—Ground Plane Figure 46. SOIC Evaluation Board—Power Plane Rev Page AD9744 ...
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... AD9744 Figure 47. SOIC Evaluation Board Assembly—Primary Side Figure 48. SOIC Evaluation Board Assembly—Secondary Side Rev Page ...
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... RP4 4 RP4 22Ω 13 22Ω RP4 6 RP4 22Ω RP4 22Ω RP4 22Ω 9 R27 R28 100Ω 100Ω Rev Page AD9744 DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X JP3 CKEXTX ...
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... CLK 13 20 CLKB IB CLKB 14 19 CCOM ACOM1 15 18 CMODE AVDD 16 CMODE 17 MODE AVDD1 AD9744LFCSP TP7 R30 10kΩ WHT CVDD JP1 MODE Figure 50. LFCSP Evaluation Board Schematic—Output Signal Conditioning CLKB JP2 CKEXT CLK AVDD C17 0.1µF SLEEP TP11 WHT R29 10kΩ ...
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... Figure 52. LFCSP Evaluation Board Layout—Primary Side Figure 53. LFCSP Evaluation Board Layout—Secondary Side Rev Page AD9744 ...
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... AD9744 Figure 54. LFCSP Evaluation Board Layout—Ground Plane Figure 55. LFCSP Evaluation Board Layout—Power Plane Rev Page ...
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... Figure 56. LFCSP Evaluation Board Layout Assembly—Primary Side Figure 57. LFCSP Evaluation Board Layout Assembly—Secondary Side Rev Page AD9744 ...
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... AD9744 OUTLINE DIMENSIONS PIN 1 0.15 0.05 COPLANARITY 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1.20 MAX 0.30 0.20 SEATING 0.19 0.09 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 58. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 18.10 (0.7126) 17.70 (0.6969 7.60 (0.2992) 7.40 (0.2913 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) SEATING 0.51 (0.0201) ...
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... AD9744ARUZ −40°C to +85°C 1 AD9744ARUZRL7 −40°C to +85°C AD9744ACP −40°C to +85°C AD9744ACPRL7 −40°C to +85°C 1 AD9744ACPZ −40°C to +85°C 1 AD9744ACPZRL7 −40°C to +85°C AD9744-EB AD9744ACP-PCB Pb-free part. 5.00 BSC SQ 0.60 MAX 24 0 ...
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... AD9744 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02913–0–4/05(B) Rev Page ...