AD5316 Analog Devices, AD5316 Datasheet - Page 15

• Manufacturer Part Number: AD5316
• Manufacturer: Analog Devices

Specifications of AD5316

• Resolution (bits): 10bit
• Dac Update Rate: 143kSPS
• Dac Settling Time: 7µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

FUNCTIONAL DESCRIPTION
The AD5306/AD5316/AD5326 are quad resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and
12 bits, respectively. Each contains four output buffer amplifiers
and is written to via a 2-wire serial interface. They operate from
single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers
provide rail-to-rail output swing with a slew rate of 0.7 V/μs. Each
DAC is provided with a separate reference input, which can be
buffered to draw virtually no current from the reference source,
or unbuffered to give a reference input range from 0.25 V to
V
can be turned off completely with a high impedance output.
DIGITAL-TO-ANALOG SECTION
The architecture of one DAC channel consists of a resistor-string
DAC followed by an output buffer amplifier. The voltage at the
V
DAC. Figure 29 shows a block diagram of the DAC architecture.
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
N is the DAC resolution.
RESISTOR STRING
The resistor string section is shown in Figure 30. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
REGISTER
DD
REF
0 to 255 for AD5306 (8 bits)
0 to 1023 for AD5316 (10 bits)
0 to 4095 for AD5326 (12 bits)
INPUT
. The devices have a power-down mode in which all DACs
pin provides the reference voltage for the corresponding
V
OUT
=
V
Figure 29. Single DAC Channel Architecture
REF
BUF
REGISTER
2
N
DAC
×
D
RESISTOR
STRING
V
REF
A
REFERENCE
BUFFER
OUTPUT BUFFER
AMPLIFIER
V
OUT
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A
DAC REFERENCE INPUTS
Each of the four DACs has a reference pin. The reference
inputs are buffered but can also be individually configured as
unbuffered. The advantage with the buffered input is the high
impedance it presents to the voltage source driving it. However,
if the unbuffered mode is used, the user can have a reference
voltage as low as 0.25 V and as high as V
restriction due to headroom and footroom of the reference
amplifier.
If there is a buffered reference in the circuit (for example,
REF192), there is no need to use the on-chip buffers of the
AD5306/AD5316/AD5326. In unbuffered mode, the input
impedance is still large at typically 180 kΩ per reference input
for 0 V to V
The buffered/unbuffered option is controlled by the BUF bit in
the control byte. The BUF bit setting applies to whichever DAC
is selected in the pointer byte.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on the value of V
of 1 is selected (GAIN = 0), the output range is 0.001 V to V
If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 V
is limited to V
The output amplifier is capable of driving a load of 2 kΩ to
GND or V
and sink capabilities of the output amplifier can be seen in the
plot in Figure 16.
The slew rate is 0.7 V/μs with a half-scale settling time to
0.5 LSB (at eight bits) of 6 μs.
REF
. Because of clamping, however, the maximum output
DD
REF
in parallel with 500 pF to GND or V
DD
mode and 90 kΩ for 0 V to 2 V
– 0.001 V.
REF
R
R
R
R
R
, GAIN, offset error, and gain error. If a gain
Figure 30. Resistor String
AD5306/AD5316/AD5326
TO OUTPUT
AMPLIFIER
DD
, since there is no
REF
mode.
DD
. The source
REF
.