AD5532 Analog Devices, AD5532 Datasheet - Page 7

• Manufacturer Part Number: AD5532
• Description: 32-Channel 14-Bit Bipolar Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5532

• Resolution (bits): 14bit
• Dac Update Rate: 45kSPS
• Dac Settling Time: 22µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

SERIAL INTERFACE
Table 4.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
CLKIN
1
2
3
4
5
6
7
8
9
10
11
12
See Figure 4, Figure 5, and Figure 6.
Guaranteed by design and characterization, not production tested.
In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulse width is 20 ns.
These numbers are measured with the load circuit of Figure 3.
SYNC should be taken low while SCLK is low for read back.
4
4
5
SYNC
SCLK
SYNC
SCLK
SYNC
SCLK
D
3
OUT
D
D
IN
IN
1 , 2
10
t
10
t
Limit at T
14
28
28
15
50
10
5
5
20
60
400
400
7
1
12
t
MSB
3
1
t
3
MSB
t
7
MIN
t
t
1
2
4
1
MSB
t
4
, T
t
2
1
MAX
t
2
t
2
1
t
(A Version)
t
2
4
t
3
2
3
3
Figure 4. 10-Bit Write (ISHA Mode and Both Readback Modes)
t
8
4
4
Figure 6. 14-Bit Read (Both Readback Modes)
t
5
4
t
t
5
6
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
Figure 5. 24-Bit Write (DAC Mode)
t
6
5
5
Rev. D | Page 7 of 20
5
6
Conditions/Comments
SCLK frequency
SCLK high pulse width
SCLK low pulse width
SYNC falling edge to SCLK falling edge setup time
SYNC low time
D
D
SYNC falling edge to SCLK rising edge setup time for read back
SCLK rising edge to D
SCLK falling edge to D
10th SCLK falling edge to SYNC falling edge for read back
24th SCLK falling edge to SYNC falling edge for DAC mode write
SCLK falling edge to SYNC falling edge setup time for read back
7
IN
IN
6
setup time
hold time
8
21
7
9
22
10
OUT
OUT
8
valid
high impedance
11
23
9
12
24
13
LSB
10
LSB
14
LSB
t
11
t
9
AD5532
1