AD5314 Analog Devices, AD5314 Datasheet

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AD5314

Manufacturer Part Number
AD5314
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD5314

Resolution (bits)
10bit
Dac Update Rate
143kSPS
Dac Settling Time
7µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

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Data Sheet
FEATURES
AD5304: 4 buffered 8-Bit DACs in 10-lead MSOP and
AD5314: 4 buffered 10-Bit DACs in 10-lead MSOP and
AD5324: 4 buffered 12-Bit DACs in 10-lead MSOP and
Low power operation: 500 μA @ 3 V, 600 μA @ 5 V
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
Double-buffered input logic
Output range: 0 V to V
Power-on reset to 0 V
Simultaneous update of outputs ( LDAC function)
Low power-, SPI®-, QSPI™-, MICROWIRE™-, and DSP-
On-chip, rail-to-rail output buffer amplifiers
Temperature range −40°C to +105°C
Qualified for automotive applications
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process controls
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
10-lead LFCSP
A, W Version: ±1 LSB INL, B Version: ±0.625 LSB INL
10-lead LFCSP
A, W Version: ±4 LSB INL, B Version: ±2.5 LSB INL
10-lead LFCSP
A, W Version: ±16 LSB INL, B Version: ±10 LSB INL
compatible 3-wire serial interface
REF
SYNC
SCLK
DIN
AD5304/AD5314/AD5324
POWER-ON RESET
2.5 V to 5.5 V, 500 μA, Quad Voltage Output
FUNCTIONAL BLOCK DIAGRAM
8-/10-/12-Bit DACs in 10-Lead Packages
REGISTER
REGISTER
REGISTER
REGISTER
INPUT
INPUT
INPUT
INPUT
LDAC
GND
V
Figure 1.
DD
REGISTER
REGISTER
REGISTER
REGISTER
DAC
DAC
DAC
DAC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
POWER-DOWN LOGIC
GENERAL DESCRIPTION
The
buffered voltage output DACs in 10-lead MSOP and 10-lead
LFCSP packages that operate from a single 2.5 V to 5.5 V supply,
consuming 500 μA at 3 V. Their on-chip output amplifiers allow
rail-to-rail output swing to be achieved with a slew rate of 0.7 V/μs.
A 3-wire serial interface is used; it operates at clock rates up to
30 MHz and is compatible with standard SPI, QSPI, MICROWIRE,
and DSP interface standards.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs can be updated simultaneously using
the software LDAC function. The parts incorporate a power-on
reset circuit, and ensure that the DAC outputs power up to 0 V
and remains there until a valid write takes place to the device.
The parts contain a power-down feature that reduces the current
consumption of the device to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1 μW in power-down mode.
1
Protected by U.S. Patent No. 5,969,657.
AD5304/AD5314/AD5324
REFIN
STRING
STRING
STRING
STRING
DAC A
DAC B
DAC C
DAC D
AD5304/AD5314/AD5324
BUFFER
BUFFER
BUFFER
BUFFER
©2011 Analog Devices, Inc. All rights reserved.
V
V
V
V
OUT
OUT
OUT
OUT
1
are quad 8-, 10-, and 12-bit
A
B
C
D
www.analog.com

Related parts for AD5314

AD5314 Summary of contents

Page 1

... AD5304: 4 buffered 8-Bit DACs in 10-lead MSOP and 10-lead LFCSP A, W Version: ±1 LSB INL, B Version: ±0.625 LSB INL AD5314: 4 buffered 10-Bit DACs in 10-lead MSOP and 10-lead LFCSP A, W Version: ±4 LSB INL, B Version: ±2.5 LSB INL AD5324: 4 buffered 12-Bit DACs in 10-lead MSOP and 10-lead LFCSP A, W Version: ± ...

Page 2

... Serial Interface ............................................................................ 14   Power-Down Mode .................................................................... 16   Microprocessor Interfacing ....................................................... 16   Applications Information .............................................................. 18   Typical Application Circuit ....................................................... 18   Decoding Multiple AD5304/AD5314/AD5324s .................... 19   Power Supply Bypassing and Grounding ................................ 20   Outline Dimensions ....................................................................... 22   Ordering Guide .......................................................................... 23   Automotive Products ................................................................. 23 8/03—Rev Rev. D Added A Version ................................................................ Universal Changes to Features ...

Page 3

... V – 0.001 V – 0.001 DD DD 0.5 0 2.5 2 Rev Page AD5304/AD5314/AD5324 unless otherwise noted. MIN MAX 2 Max Unit Test Conditions/Comments Bits ±0.625 LSB ±0.25 LSB Guaranteed monotonic by design over all codes Bits ±2.5 LSB ±0.5 ...

Page 4

... Temperature range ( Version): −40°C to +105°C; typical at +25° specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5304 (Code 8 to Code 248); AD5314 (Code 28 to Code 995); AD5324 (Code 115 to Code 3981). 5 Guaranteed by design and characterization, not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative ...

Page 5

... DB0 Figure 2. Serial Interface Timing Diagram Rev Page AD5304/AD5314/AD5324 Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge ...

Page 6

... AD5304/AD5314/AD5324 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. 1 Parameter Rating V to GND –0 Digital Input Voltage to GND –0 Reference Input Voltage to GND –0 through GND –0 OUT OUT Operating Temperature Range Industrial ( Version) – ...

Page 7

... THERE IS A CONNECTION VIA THE GND PIN. OUT th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write Rev Page AD5304/AD5314/AD5324 SYNC DD AD5304 SCLK OUT AD5314 AD5324 3 8 DIN OUT TOP VIEW GND OUT (Not to Scale) REFIN 5 ...

Page 8

... CODE Figure 8. AD5304 Typical DNL Plot T = 25° 200 400 600 800 CODE Figure 9. AD5314 Typical DNL Plot T = 25° 500 1000 1500 2000 2500 3000 CODE Figure 10. AD5324 Typical DNL Plot 250 1000 ...

Page 9

... REF 120 600 500 400 300 200 100 0 80 120 Rev Page AD5304/AD5314/AD5324 T = 25°C A GAIN ERROR REF OFFSET ERROR (V) DD Figure 14. Offset Error and Gain Error vs SOURCE 3V SOURCE 3V SINK ...

Page 10

... AD5304/AD5314/AD5324 600 –40°C 500 +25°C 400 +105°C 300 200 100 0 2.5 3.0 3.5 4.0 V (V) DD Figure 17. Supply Current vs. Supply Voltage 0.5 0.4 0.3 0.2 +25°C 0.1 0 2.5 3.0 3.5 4.0 V (V) DD Figure 18. Power-Down Current vs. Supply Voltage 1000 T = 25°C A 900 800 700 600 500 400 0 0.5 1.0 1.5 2.0 2.5 3.0 V (V) LOGIC Figure 19. Supply Current vs. Logic Input Voltage ...

Page 11

... FREQUENCY (Hz) Figure 25. Multiplying Bandwidth (Small-Signal Frequency Response 550 600 = 100k 1M 10M Rev Page AD5304/AD5314/AD5324 0. 25°C A 0.01 0 –0.01 –0. (V) REF Figure 26. Full-Scale Error vs. V REF 150ns/DIV Figure 27 ...

Page 12

... AD5304/AD5314/AD5324 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity (INL measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. Typical INL vs. code plots can be seen in Figure 5, Figure 6, and Figure 7. ...

Page 13

... CODES AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR Figure 28. Transfer Function with Negative Offset GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE POSITIVE OFFSET Rev Page AD5304/AD5314/AD5324 GAIN ERROR PLUS OFFSET ERROR ACTUAL IDEAL DAC CODE Figure 29. Transfer Function with Positive Offset ...

Page 14

... Figure 15. The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at eight bits μs. POWER-ON RESET The AD5304/AD5314/AD5324 are provided with a power-on reset V A function, so that they power defined state. The power-on OUT state uses normal operation and an output voltage set ...

Page 15

... Only addressed input register is updated. There is no change in the content of the DAC registers. The AD5324 uses all 12 bits of DAC data; the AD5314 uses 10 bits and ignores the 2 LSB Bits. The AD5304 uses eight bits and ignores the last four bits. The data format is straight binary, with all 0s ...

Page 16

... CIRCUITRY Figure 35. Output Stage during Power-Down MICROPROCESSOR INTERFACING AD5304/AD5314/AD5324 to ADSP-21xx Figure 36 shows a serial interface between the AD5304/AD5314/ AD5324 and the ADSP-21xx family. The ADSP-21xx is set up to operate in the SPORT transmit alternate framing mode. The ADSP-21xx sport is programmed through the SPORT control register and must be configured as follows: internal clock operation, active-low framing, and 16-bit word length ...

Page 17

... Data is transmitted MSB first. To load data to the AD5304/ AD5314/AD5324, PC7 is left low after the first eight bits are transferred, a second serial write operation is performed to the DAC, and PC7 is taken high at the end of this procedure ...

Page 18

... AD5304/AD5314/AD5324 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT The AD5304/AD5314/AD5324 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780 and REF192 (2 ...

Page 19

... AD5304/AD5314/AD5324 as a Digitally Programmable Window Detector A digitally programmable upper/lower limit detector using two DACs in the AD5304/AD5314/AD5324 is shown in Figure 44. DD The upper and lower limits for the test are loaded to DAC A REFIN and DAC B, which, in turn, set the limits on the CMP04. If the signal at the V an LED indicates the fail condition ...

Page 20

... The printed circuit board on which the AD5304/AD5314/AD5324 is mounted is designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5304/AD5314/AD5324 are in a system where multiple devices require an AGND-to-DGND connection, the connection is made at one point only. The star ground point is established as close as possible to the device. The AD5304/AD5314/AD5324 has ample supply bypassing of 10 μ ...

Page 21

... Rev Page AD5304/AD5314/AD5324 Additional Pin Functions Package GAIN HBEN CLR ✓ ✓ TSSOP ✓ ✓ TSSOP ✓ ✓ TSSOP ✓ ✓ ✓ TSSOP ✓ TSSOP ✓ ✓ ...

Page 22

... AD5304/AD5314/AD5324 OUTLINE DIMENSIONS IDENTIFIER PIN 1 INDEX AREA 0.80 0.75 0.70 SEATING PLANE 3.10 3.00 2.90 5. 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.15 0.23 6° 0.30 0.05 0.13 0° 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 3.10 3.00 SQ 2.90 6 0.50 0.40 0.30 5 TOP VIEW BOTTOM VIEW 0.05 MAX 0.02 NOM 0.30 0.20 REF ...

Page 23

... W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5314WARMZ-REEL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications ...

Page 24

... AD5304/AD5314/AD5324 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00929-0-9/11(H) Rev Page Data Sheet ...

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