AD5542 Analog Devices, AD5542 Datasheet - Page 4

• Manufacturer Part Number: AD5542
• Description: 2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD5542

• Resolution (bits): 16bit
• Dac Update Rate: 1.5MSPS
• Dac Settling Time: 1µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5541/AD5542
Parameter
POWER REQUIREMENTS
1
2
3
TIMING CHARACTERISTICS
V
+85°C, unless otherwise noted.
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
1
2
3
4
5
6
7
8
9
9
10
11
12
Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C.
Reference input resistance is code-dependent, minimum at 0x8555.
Guaranteed by design, not subject to production test.
Guaranteed by design and characterization. Not production tested
All input signals are specified with t
DD
V
I
Power Dissipation
DD
DD
= 2.7 V to 5.5 V ±10%, V
1
1, 2
LDAC*
*AD5542 ONLY. CAN BE TIED PERMANENTLY LOW IF REQUIRED.
SCLK
DIN
CS
Limit
25
40
20
20
10
15
30
20
15
4
7.5
30
30
30
t
12
REF
R
t
= t
6
= 2.5 V, V
F
= 1 ns/V and timed from a voltage level of (V
t
DB15
t
4
8
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t
5
INH
= 3 V and 90% of V
Min
2.7
Typ
125
0.625
t
2
Figure 3. Timing Diagram
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (V
Data hold time (V
LDAC pulse width
CS high to LDAC low setup
CS high time between active periods
Rev. E | Page 4 of 20
t
1
DD
t
3
, V
INL
INL
+ V
= 0 V and 10% of V
Max
5.5
150
0.825
INH
)/2.
INH
INH
t
7
= 90% of V
= 3V, V
t
5
t
11
INL
t
10
Unit
V
μA
mW
= 0 V)
DD
DD
, V
, AGND = DGND = 0 V; −40°C < T
INL
= 10% of V
Test Conditions
Digital inputs at rails
DD
)
A
<