AD5323 Analog Devices, AD5323 Datasheet - Page 17

• Manufacturer Part Number: AD5323
• Description: 2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD5323

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

SERIAL INTERFACE
The AD5303/AD5313/AD5323 are controlled over a versatile,
3-wire serial interface, which operates at clock rates up to
30 MHz and is compatible with SPI, QSPI, MICROWIRE,
and DSP interface standards.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. Data is loaded into
the device as a 16-bit word under the control of a serial clock
input, SCLK. The timing diagram for this operation is shown in
Figure 5. The 16-bit word consists of four control bits followed
by 8 /10 /12 bits of DAC data, depending on the device type.
The first bit loaded is the MSB (Bit 15), which determines whether
the data is for DAC A or DAC B. Bit 14 determines the output
range (0 V to V
operating mode of the DAC.
Table 6. Control Bits
Bit
15
14
13
12
The remaining bits are DAC data bits, starting with the MSB
and ending with the LSB. The AD5323 uses all 12 bits of DAC
data; the AD5313 uses 10 bits and ignores the 2 LSBs. The
AD5303 uses eight bits and ignores the last four bits. The data
format is straight binary, with all 0s corresponding to 0 V output,
and all 1s corresponding to full-scale output (V
The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can be transferred
into the device only while SYNC is low. To start the serial data
transfer, SYNC should be taken low, observing the minimum
SYNC to SCLK rising edge setup time, t
serial data is shifted into the device’s input shift register on the
falling edges of SCLK for 16 clock pulses. Any data and clock
pulses after the 16th are ignored, and no further serial data
transfer occurs until SYNC is taken high and low again.
SYNC may be taken high after the falling edge of the 16th SCLK
pulse, observing the minimum SCLK falling edge to SYNC
rising edge time, t
Name
A/B
GAIN
PD1
PD0
Function
0: data written to DAC A
1: data written to DAC B
0: output range of 0 V to V
1: output range of 0 V to 2 V
Mode bit
Mode bit
REF
7
or 0 V to 2 V
.
REF
). Bit 13 and Bit 12 control the
4
REF
. After SYNC goes low,
REF
REF
Power-On
Default
N/A
0
0
0
− 1 LSB).
Rev. B | Page 17 of 28
After the end of serial data transfer, data is automatically
transferred from the input shift register to the input register
of the selected DAC. If SYNC is taken high before the 16th
falling edge of SCLK, the data transfer is aborted and the input
registers are not updated.
When data has been transferred into both input registers, the
DAC registers of both DACs may be simultaneously updated,
by taking LDAC low. CLR is an active low, asynchronous clear
that clears the input and DAC registers of both DACs to all 0s.
LOW POWER SERIAL INTERFACE
To reduce the power consumption of the device even further,
the interface only powers up fully when the device is being
written to. As soon as the 16-bit control word has been written
to the part, the SCLK and DIN input buffers are powered down.
They only power up again following a falling edge of SYNC .
DOUBLE-BUFFERED INTERFACE
The DACs all have double-buffered interfaces consisting of two
banks of registers—input registers and DAC registers. The input
register is connected directly to the input shift register and the
digital code is transferred to the relevant input register on com-
pletion of a valid write sequence. The DAC register contains the
digital code used by the resistor string.
Access to the DAC register is controlled by the LDAC function.
When LDAC is high, the DAC register is latched and the input
register may change state without affecting the contents of the
DAC register. However, when LDAC is brought low, the DAC
register becomes transparent and the contents of the input reg-
ister are transferred to it.
This is useful if the user requires simultaneous updating of
both DAC outputs. The user may write to both input registers
individually and then, by pulsing the LDAC input low, both
outputs update simultaneously.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when LDAC
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5303/AD5313/AD5323,
the part only updates the DAC register if the input register has
been changed since the last time the DAC register was updated,
thereby removing unnecessary digital crosstalk.
AD5303/AD5313/AD5323