AD9764 Analog Devices, AD9764 Datasheet
AD9764
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AD9764 Summary of contents
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... The AD9764 is available in 28-lead SOIC and TSSOP packages specified for operation over the industrial temperature range. PRODUCT HIGHLIGHTS 1. The AD9764 is a member of the TxDAC product family that provides an upward or downward component selection path based on resolution ( bits), performance and cost. ...
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... AD9764–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL + MIN MAX Differential Nonlinearity (DNL + MIN MAX ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current ...
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... Max 2.5 2 –78 –74 –72 –75 – AD9764 Units MSPS pA/ Hz pA/ Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9764 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... DB9 5 24 AVDD AD9764 DB8 6 23 COMP2 TOP VIEW (Not to Scale) DB7 OUTA 8 DB6 I 21 OUTB DB5 9 ACOM 20 DB4 10 COMP1 19 DB3 ADJ DB2 12 17 REFIO DB1 13 16 REFLO DB0 SLEEP CONNECT PIN FUNCTION DESCRIPTIONS –5– AD9764 ...
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... T . For MIN MAX +5V 0.1 F REFLO COMP1 AVDD ACOM AD9764 50pF PMOS CURRENT SOURCE ARRAY SEGMENTED SWITCHES LSB FOR DB13–DB5 SWITCHES LATCHES DIGITAL DATA ...
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... MSPS 10MHz @ 50 MSPS 50 –30 –25 –20 –15 –10 –5 A – dBFS OUT Figure 10. Single-Tone SFDR vs OUT OUT CLOCK –7– AD9764 = +25 C, SFDR up to Nyquist, unless otherwise noted –6dBFS 85 –12dBFS 0dBFS FREQUENCY – ...
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... AD9764 –70 –75 2ND HARMONIC –80 3RD HARMONIC –85 4TH HARMONIC –90 –95 000.0E+0 40.0E+6 80.0E+6 120.0E+6 Figure 12. THD vs CLOCK MHz OUT 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0 4000 8000 12000 16000 CODE Figure 15. Typical INL 50MSPS CLK – 1.25MHz OUT SFDR = 78dBc – ...
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... CLOCK FUNCTIONAL DESCRIPTION Figure 21 shows a simplified block diagram of the AD9764. The AD9764 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB current source ...
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... IREF between OUTFS 62.5 A and 625 A. The wide adjustment span of I provides several application benefits. The first benefit relates directly to the power dissipation of the AD9764, which is pro- portional to I second benefit relates to the 20 dB adjustment, which is useful for system gain control purposes. ...
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... CMOS process. Operation ARRAY beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9764. The posi- tive output compliance range is slightly dependent on the full- scale output current, I –11– ...
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... Figure 8. The noise performance of the AD9764 is affected by the digital supply (DVDD), output frequency, and increases with increasing clock rate as shown in Figure 13. Operating the AD9764 with low voltage logic levels between 3 V and 3.3 V will slightly reduce the amount of on-chip digital noise mA. ...
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... Since the AD9764 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9764 with reduced logic swings and a corresponding digital supply (DVDD) will result in the lowest data feedthrough and on-chip digital noise ...
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... In this case, AVDD, which is the positive analog supply for both the AD9764 and the op amp, is also used to level-shift the differ- ential output of the AD9764 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...
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... AD9764 evaluation board. Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9764 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a REV ...
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... SFDR performance. However, unlike most DACs, which employ an R-2R ladder for the lower bit current segmentation, the AD9764 (as well as other TxDAC members) exhibits an improvement in distortion performance as the amplitude of a single tone is re- duced from its full-scale level. This improvement in distortion performance at reduced signal levels is evident if one compares the SFDR performance vs ...
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... AD9764 in any application where high resolution, high speed conversion is required. /16. This board allows the user the flexibility to operate the AD9764 CLOCK /10) in various configurations. Possible output configurations include CLOCK transformer coupled, resistor terminated, inverting/noninverting /2 ...
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... AD9764 Figure 41. Evaluation Board Schematic –18– REV. B ...
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... REV. B Figure 42. Silkscreen Layer—Top Figure 43. Component Side PCB Layout (Layer 1) –19– AD9764 ...
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... AD9764 Figure 44. Ground Plane PCB Layout (Layer 2) Figure 45. Power Plane PCB Layout (Layer 3) –20– REV. B ...
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... REV. B Figure 46. Solder Side PCB Layout (Layer 4) Figure 47. Silkscreen Layer—Bottom –21– AD9764 ...
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... AD9764 PIN 1 0.0118 (0.30) 0.0040 (0.10) PIN 1 0.006 (0.15) 0.002 (0.05) SEATING OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65 0.3937 (10.00) 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) SEATING 0.0125 (0.32) (1.27) PLANE 0.0138 (0.35) 0.0091 (0.23) BSC 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60 ...