AD9760 Analog Devices, AD9760 Datasheet

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AD9760

Manufacturer Part Number
AD9760
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD9760

Resolution (bits)
10bit
Dac Update Rate
125MSPS
Dac Settling Time
35ns
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Current Out
Dac Input Format
Par

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a
PRODUCT DESCRIPTION
The AD9760 and AD9760-50 are the 10-bit resolution members
of the TxDAC series of high performance, low power CMOS
digital-to-analog converters (DACs). The AD9760-50 is a lower
performance option that is guaranteed and specified for 50 MSPS
operation. The TxDAC family that consists of pin compatible 8-,
10-, 12- and 14-bit DACs is specifically optimized for the trans-
mit signal path of communication systems. All of the devices
share the same interface options, small outline package and
pinout, thus providing an upward or downward component
selection path based on performance, resolution and cost. Both
the AD9760 and AD9760-50 offer exceptional ac and dc
performance while supporting update rates up to 125 MSPS
and 60 MSPS respectively.
The AD9760’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW without a significant degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 25 mW.
The AD9760 is manufactured on an advanced CMOS process. A
segmented current source architecture is combined with a propri-
etary switching technique to reduce spurious components and
enhance dynamic performance. Edge-triggered input latches and a
1.2 V temperature compensated bandgap reference have been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
TxDAC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
10-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 40 MHz Output: 52 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:
Direct Digital Synthesis (DDS)
Instrumentation
Basestations
Set Top Boxes
Digital Radio Link
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
The AD9760 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9760 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier that provides a wide
(>10:1) adjustment span allows the AD9760 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9760 may oper-
ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9760 is available in a 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9760 is a member of the TxDAC product family that
2. Manufactured on a CMOS process, the AD9760 uses a pro-
3. On-chip, edge-triggered input CMOS latches interface readily
4. A flexible single-supply operating range of 2.7 V to 5.5 V and
5. The current output(s) of the AD9760 can be easily config-
CLOCK
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.
prietary switching technique that enhances dynamic perfor-
mance beyond what was previously attainable by higher
power/cost bipolar or BiCMOS devices.
to +3 V and +5 V CMOS logic families. The AD9760 can
support update rates up to 125 MSPS.
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9760 to operate at reduced power levels.
ured for various single-ended or differential circuit topologies.
R
SET
0.1 F
+5V
FUNCTIONAL BLOCK DIAGRAM
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
+1.20V REF
TxDAC
World Wide Web Site: http://www.analog.com
REFLO
DIGITAL DATA INPUTS (DB9–DB0)
SEGMENTED
SWITCHES
10-Bit, 125 MSPS
50pF
®
LATCHES
D/A Converter
COMP1
0.1 F
CURRENT
© Analog Devices, Inc., 2000
SOURCE
ARRAY
SWITCHES
LSB
AD9760
+5V
AVDD
AD9760
COMP2
ACOM
I
I
OUTA
OUTB
0.1 F

Related parts for AD9760

AD9760 Summary of contents

Page 1

... The AD9760 is available in a 28-lead SOIC and TSSOP packages specified for operation over the industrial temperature range. PRODUCT HIGHLIGHTS 1. The AD9760 is a member of the TxDAC product family that provides an upward or downward component selection path based on resolution ( bits), performance and cost. ...

Page 2

... AD9760/AD9760-50–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) MONOTONICITY ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance Range Output Resistance Output Capacitance ...

Page 3

... Min Typ Max 2.5 2 N/A N/A N/A N N/A –73 –76 –70 –71 –68 –71 N/A AD9760 Units MSPS pA/√Hz pA/√Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...

Page 4

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9760 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 5

... DCOM 4 DB6 DB5 24 AVDD AD9760 DB4 6 23 COMP2 TOP VIEW (Not to Scale) DB3 OUTA DB2 OUTB 9 DB1 20 ACOM 10 19 DB0 COMP1 ADJ REFIO REFLO SLEEP CONNECT PIN FUNCTION DESCRIPTIONS –5– AD9760 ...

Page 6

... Total Harmonic Distortion THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured output signal expressed as a percentage or in decibels (dB). +5V 0.1 F REFLO COMP1 AVDD ACOM AD9760 50pF PMOS COMP2 CURRENT SOURCE ARRAY I LSB SEGMENTED SWITCHES I FOR DB11– ...

Page 7

... A – dBFS OUT Figure 10. Single-Tone SFDR vs OUT OUT CLOCK –7– AD9760 = +25 C, SFDR up to Nyquist, unless otherwise noted –6dBFS 75 –12dBFS 70 0dBFS 0.00 2.00 4.00 6.00 8.00 10.00 FREQUENCY – MHz Figure 5. SFDR vs. f ...

Page 8

... AD9760 –70 –75 2ND HARMONIC –80 3RD HARMONIC –85 4TH –90 HARMONIC – 100 120 140 FREQUENCY – MSPS Figure 12. THD vs CLOCK MHz OUT 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 125 250 375 500 625 750 875 1000 CODE Figure 15 ...

Page 9

... A – dBFS OUT Figure 28. Single-Tone SFDR vs OUT OUT CLOCK –9– AD9760 = +25 C, SFDR up to Nyquist, unless otherwise noted –6dBFS 75 70 –12dBFS 65 0dBFS 0.00 2.00 4.00 6.00 8.00 10.00 FREQUENCY – MHz Figure 23. SFDR vs. f ...

Page 10

... AD9760 –70 –75 2ND HARMONIC 3RD –80 HARMONIC –85 –90 4TH HARMONIC – 100 120 140 FREQUENCY – MSPS Figure 30. THD vs. f CLOCK MHz OUT 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 125 250 375 500 625 750 875 1000 CODE Figure 33 ...

Page 11

... FUNCTIONAL DESCRIPTION Figure 39 shows a simplified block diagram of the AD9760. The AD9760 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 equal currents that make up the 5 most sig- nificant bits (MSBs). The next 4 bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB current source ...

Page 12

... MΩ) of REFIO minimizes any loading of the external reference. and REFERENCE CONTROL AMPLIFIER OUTA The AD9760 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, I (7) The control amplifier is configured as a V-I converter as shown and ...

Page 13

... single-ended unipolar output is desirable, CURRENT I should be selected. OUTA SOURCE ARRAY The distortion and noise performance of the AD9760 can be enhanced when the AD9760 is configured for differential opera- tion. The common-mode error sources of both I I 625A can be significantly reduced by the common-mode rejection of a REF transformer or differential amplifier ...

Page 14

... The drivers of the digital data interface circuitry should be specified to meet the mini- mum setup and hold times of the AD9760 as well as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feedthrough and noise ...

Page 15

... COMP1. With a nominal value of 0.1 µF, the AD9760 takes less than 5 µs to power down and approximately 3. power back up. Note, the SLEEP MODE should not be used when the external control amplifier is used as shown in Figure 45 ...

Page 16

... In this case, AVDD which is the positive analog supply for both the AD9760 and the op amp is also used to level-shift the differ- ential output of the AD9760 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...

Page 17

... Figure 55. Differential LC Filter for Single + Applications Maintaining low noise on power supplies and ground is critical to obtain optimum results from the AD9760. If properly imple- mented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current transport, etc. In mixed signal design, the analog and digital portions of ...

Page 18

... D/A converter. Careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9760 in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9760 in various configurations. Possible output configurations include and R . ...

Page 19

... REV. B Figure 59. Evaluation Board Schematic –19– AD9760 ...

Page 20

... AD9760 Figure 60. Silkscreen Layer—Top Figure 61. Component Side PCB Layout (Layer 1) –20– REV. B ...

Page 21

... REV. B Figure 62. Ground Plane PCB Layout (Layer 2) Figure 63. Power Plane PCB Layout (Layer 3) –21– AD9760 ...

Page 22

... AD9760 Figure 64. Solder Side PCB Layout (Layer 4) Figure 65. Silkscreen Layer—Bottom –22– REV. B ...

Page 23

... PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) SEATING 0.0125 (0.32) (1.27) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) (RU-28) 0.386 (9.80) 0.378 (9.60 PIN 1 0.0433 (1.10) MAX 0.0118 (0.30) 0.0256 (0.65) 0.0079 (0.20) BSC 0.0075 (0.19) 0.0035 (0.090) –23– AD9760 0.0291 (0.74) 45 0.0098 (0.25) 0.0500 (1.27 0.0157 (0.40) 0.028 (0.70 0.020 (0.50) ...

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