AD8802 Analog Devices, AD8802 Datasheet
AD8802
Specifications of AD8802
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AD8802 Summary of contents
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... The serial-data-input word is decoded where the first 4 bits determine the address of the DAC latches to be loaded with the last 8 bits of data. The AD8802/ AD8804 consumes only 10 A from 5 V power supplies. In ad- dition, in shutdown mode reference input current consumption is also reduced while saving the DAC latch settings for use after return to normal operation ...
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... AD8802/AD8804–SPECIFICATIONS Parameter STATIC ACCURACY Specifications apply to all DACs Resolution Differential Nonlinearity Error Integral Nonlinearity Error Full-Scale Error Zero Code Error DAC Output Resistance Output Resistance Match REFERENCE INPUT 2 Voltage Range REFH Input Resistance 3 REFL Input Resistance 3 Reference Input Capacitance DIGITAL INPUTS ...
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... Maximum Junction Temperature (T MAX +150 C J Storage Temperature . . . . . . . . . . . . . . . . . . – +150 C Lead Temperature (Soldering, 10 sec +300 C Package Power Dissipation . . . . . . . . . . . . (T Thermal Resistance JA, SOIC (SOL-20 C/W P-DIP (N-20 C/W TSSOP-20 (RU-20 155 C/W AD8802 PIN DESCRIPTIONS Pin Name Description 1 V Common DAC Reference Input REF 2 O1 DAC Output #1, addr = 0000 3 ...
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... AD8802/AD8804–Typical Performance Characteristics + +5V REFH REFL 0.5 0.25 0 –0.25 –0.5 –0.75 – 128 160 CODE – Decimal Figure 1. INL vs. Code 1 0. + +5V REFH REFL 0.25 0 –0.25 –0.5 –0.75 – 128 160 CODE – Decimal Figure 2 ...
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... OUT1 5mV/DIV CS 5V/DIV 10k 100k 0.01 5µs 0.005 + +5V REF –0.005 –0.01 0 Figure 12. Zero-Scale Error Accelerated by Burn-In –5– AD8802/AD8804 OUTPUT1 +5V DD 100 V = +5V REF 1MHz 10 0% 10mV 200ns TIME – 0.2µs/DIV 5mV 1µs 100 ...
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... The AD8802 offers a midscale preset activated by the RS pin simplifying initial setting conditions at first power-up. The AD8804 has both a V and a V pin to establish indepen- REFH REFL dent positive full-scale and zero-scale settings to optimize reso- lution. Both parts offer a power shutdown SHDN which places ...
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... REFH REFL The reference input pins set the output voltage range of all twelve DACs. In the case of the AD8802 only the V available to establish a user designed full-scale output voltage. The external reference voltage can be any value between 0 and V but must not exceed the V supply voltage ...
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... REFL Figure 22. Buffering the AD8802/AD8804 Output Increasing Output Voltage Swing An external amplifier can also be used to extend the output volt- age swing beyond the power supply rails of the AD8802/AD8804. AD8802/ This technique permits an easy digital interface for the DAC, AD8804 while expanding the output swing to take advantage of higher voltage external power supplies. For example, DAC A of Fig- ure 23 is configured to swing from – ...
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... RS-232 communications interface), the AD8802/AD8804 can easily be addressed in software. Twelve data bits are required to load a value into the AD8802/ AD8804 (4 bits for the DAC address and 8 bits for the DAC value). If more than 12 bits are transmitted before the Chip Se- lect input goes high, the extra (i ...
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... AD8802/AD8804 ; ; This subroutine loads an AD8802/AD8804 DAC from an 8051 microcomputer, ; using the 8051’s serial port in MODE 0 (Shift Register Mode). ; The DAC value is stored at location DAC_VAL ; The DAC address is stored at location DAC_ADDR ; ; Variable declarations ; PORT1 DATA DAC_VALUE DATA DAC_ADDR DATA SHIFT1 DATA ...
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... This 8051 C subroutine loads an AD8802 or AD8804 DAC with an 8-bit value, ; using the 8051’s parallel port #1. ; The DAC value is stored at location DAC_VALUE ; The DAC address is stored at location DAC_ADDR ; ; Variable declarations PORT1 DATA DAC_VALUE DATA DAC_ADDR DATA LOOPCOUNT DATA ; ORG LD_8804: ORL ...
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... SPI data register; Read-Buffer; Write-Shifter SDI1 is encoded from SDI2 is encoded from 00H to FFH AD8802/AD8804 requires two 8-bit loads; upper 4 bits of SDI1 are ignored. AD8802/AD8804 address bits in last four LSBs of SDI1. SDI packed byte 1 “0,0,0,0;A3,A2,A1,A0” SDI packed byte 2 “DB7–DB4;DB3–DB0” ...
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... STAA SDI1 * * Enter Contents of SDI2 Data Register * LDAA $0001 STAA SDI2 * LDX #SDI1 LDY #$1000 * * Reset AD8802 to one-half scale (AD8804 does not have a Reset input) * BCLR PORTC,Y $02 BSET PORTC,Y $ Get AD8802/04 ready for data input * BCLR PORTD,Y $02 * TFRLP LDAA 0,X STAA ...
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... Now notice that the normal + GND voltage range of the AD8802/AD8804 does not cover the 3 –1.2 V operational gain control range of the SSM2018T. To cover the operating gain range fully and not exceed the maxi- mum specified power supply rating requires the O1 output of AD8802/AD8804 to be level shifted down ...
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... V to span the central the gain range. An overrange and underrange provided whatever the selected range. The gain-control response time is less than 1 s for change. The settling time of the AD8802/AD8804 to within a 1/2 LSB band is 0.6 s making it an excellent choice for con- trol of the AD603. ...
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... AD8802/AD8804 IN +10V 10µF 1/2 OP279 30k 2.0V 20k 20-Pin Plastic DIP Package (N-20) 1.07 (27.18) MAX 20 11 0.255 (6.477) 0.245 (6.223 0.060 (1.52) PIN 1 0.015 (0.38) 0.145 (3.683) MAX 0.125 (3.175) MIN SEATING 0.021 (0.533) 0.11 (2.79) 0.065 (1.66) PLANE 0.015 (0.381) 0.09 (2.28) 0.045 (1.15) 0.006 (0.15) 0.002 (0.05) SEATING PLANE +10V 0.1µF 0.1µF 0.1µ ...