AD7248A Analog Devices, AD7248A Datasheet
AD7248A
Specifications of AD7248A
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AD7248A Summary of contents
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... The AD7245A accepts 12-bit parallel data that is loaded into the input latch on the rising edge WR. The AD7248A has an 8-bit-wide data bus with data loaded to the input latch in two write operations. For both parts, an asynchronous LDAC signal transfers data from the input latch to the DAC latch and updates the analog output ...
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... AD7245A/AD7248A–SPECIFICATIONS AGND = DGND = 100 pF. All specifications Parameter STATIC PERFORMANCE Resolution 3 Relative Accuracy @ 25° MIN MAX MIN MAX 3 Differential Nonlinearity 3 Unipolar Offset Error @ 25° MIN MAX 3 Bipolar Zero Error @ 25° MIN MAX 3, 6 DAC Gain Error ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7245A/AD7248A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... DAC and output amplifier present for all codes and is measured with a code of 2048 (decimal) in the DAC register. SINGLE SUPPLY LINEARITY AND GAIN ERROR The output amplifier of the AD7245A/AD7248A can have a Relative Package true negative offset even when the part is operated from a single ...
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... CONNECT AD7245A/AD7248A Description Write Input (Active LOW). This is used in conjunction with CS to write data into the input latch of the AD7245A. Load DAC Input (Active LOW). This is an asynchronous input which when active transfers data from the input latch to the DAC latch ...
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... LOW). This selects the lower 8 bits of the input latch. Write Input. This is used in conjunction with CSMSB and CSLSB to load data into the input latch of the AD7248A. Load DAC Input (Active LOW). This is an asynchronous input which when active transfers data from the input latch to the DAC latch ...
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... 100mV p-p SIGNAL 0 20k 50k 50 POWER SUPPLY DECOUPLING CAPACITORS ARE 10 F AND 0.1 F 100 AD7245A/AD7248A – TEMPERATURE – C OUTPUT WITH ALL DECOUPLING 0s ON DAC NO DECOUPLING OUTPUT WITH ALL DECOUPLING 1s ON DAC NO DECOUPLING = 15V WITH 100 ...
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... The control inputs sink higher currents (150 µA max result of the fast digital interfacing. Internal input protection of all logic inputs is achieved by on-chip distributed diodes. The AD7245A/AD7248A features a very low digital feedthrough figure output range. This is due to the volt- age mode configuration of the DAC. Most of the impulse is actually as a result of feedthrough across the package. INTERFACE LOGIC INFORMATION— ...
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... DAC LATCH CSMSB, CSLSB and WR control the loading of data from the external data bus to the input latch. The eight data inputs on the AD7248A accept right justified data. This data is loaded to INPUT LATCH the input latch in two separate write operations. CSLSB and WR control the loading of the lower 8-bits into the 12-bit wide latch ...
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... VALID DATA DATA IN An alternate scheme for writing data to the AD7248A is to tie the CSMSB and LDAC inputs together. In this case exercising CSLSB and WR latches the lower 8 bits into the input latch. The second write, which exercises CSMSB, WR and LDAC loads the upper 4-bit nibble to the input latch and at the same time transfers the 12-bit data to the DAC latch ...
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... V × The VN0300M is placed in the feedback of the AD7245A/ 2048 AD7248A amplifier. The entire circuit can be operated in single 2047 supply by tying the V × 2048 The sink current, I ...
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... AD7245A/AD7248A Since the tolerance value on the reference voltage of the AD7245A/ AD7248A is ± 0.2%, then the absolute value of I ± 0.2% from device to device for a fixed value of R1. Because the input bias current of the AD7245A/AD7248A’s op amp is only of the order of picoamps, its effect on the sink cur- rent is negligible ...
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... Data is first written to the AD7248A input latch in two write LDAC operations. Either the high byte or the low byte data can be WR written first to the AD7248A input latch. A write to the AD7248A DB11 DAC latch address transfers the input latch data to the DAC DB0 latch and updates the output voltage ...
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... Puls- ing the P3.1 line, after the high byte data has been set up on Port 1, updates the output of the AD7248A. The WR input of the AD7248A can be hardwired low in this application because spurious address strobes on CSLSB and CSMSB do not occur. ...
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... VIEW (1.27) 11 BSC 0.456 (11.58) 45 TYP 0.200 0.450 (11.43) (5.08) 0.495 (12.57) BSC 0.485 (12.32) AD7245A/AD7248A 0.130 (3.30) 0.128 (3.25) 0.015 (0.381) 0.008 (0.204) 24-Lead Cerdip (Q-24 0.295 (7.493) MAX 1 12 0.070 (1.78) 0.320 (8.128) 0.030 (0.76) 0.290 (7.366) 1.290 (32.77) MAX 0.180 (4.572) MAX 0.070 (1.778) ...
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... Changed B and T Versions of V Power Requirements from –11.4/–15.75 to –10.8/–16.5 for V max . . . . . . . . . . . . . . . . . . . . . 2 SS Change to Note 1 and Note 9 of Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Change to Note 2 in Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Changes to R-24 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MECHANICAL INFORMATION —AD7248A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.32 (8.128) 0.29 (7.366) 0.18 (4.57) 0.20 (5.0) ...