ADUC842 Analog Devices, ADUC842 Datasheet - Page 52

• Manufacturer Part Number: ADUC842
• Description: Precision Analog Microcontroller: 16MIPS 8052 Flash MCU + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC842

• Mcu Core: 8052
• Mcu Speed (mips): 16
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 8
• Other: PWM

ADuC841/ADuC842/ADuC843
POWER SUPPLY MONITOR
As its name suggests, the power supply monitor, once enabled,
monitors the DV
ADuC843. It indicates when any of the supply pins drops below
one of two user selectable voltage trip points, 2.93 V and 3.08 V.
For correct operation of the power supply monitor function,
AV
controlled via the PSMCON SFR. If enabled via the IEIP2 SFR,
the monitor interrupts the core using the PSMI bit in the
PSMCON SFR. This bit is not cleared until the failing power
supply has returned above the trip point for at least 250 ms.
This monitor function allows the user to save working registers
to avoid possible data loss due to the low supply condition, and
also ensures that normal code execution does not resume until a
safe supply level has been well established. The supply monitor
Table 22. PSMCON SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
DD
must be equal to or greater than 2.7 V. Monitor function is
Name
----
CMPD
PSMI
TPD1
TPD0
----
----
PSMEN
DD
supply on the ADuC841/ADuC842/
Description
Reserved.
DV
This is a read-only bit that directly reflects the state of the DV
Read 1 indicates that the DV
Read 0 indicates that the DV
Power Supply Monitor Interrupt Bit.
This bit is set high by the MicroConverter if either CMPA or CMPD is low, indicating low analog or digital supply. The
PSMI bit can be used to interrupt the processor. Once CMPD and/or CMPA return (and remain) high, a 250 ms
counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the user.
However, if either comparator output is low, it is not possible for the user to clear PSMI.
DV
These bits select the DV
TPD1
0
0
1
1
Reserved.
Reserved.
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the power supply monitor circuit.
Cleared to 0 by the user to disable the power supply monitor circuit.
DD
DD
Comparator Bit.
Trip Point Selection Bits.
TPD0
0
1
0
1
DD
trip point voltage as follows:
Selected DV
Reserved
3.08
2.93
Reserved
DD
DD
supply is above its selected trip point.
supply is below its selected trip point.
Rev. 0 | Page 52 of 88
DD
Trip Point (V)
is also protected against spurious glitches triggering the
interrupt circuit.
Note that the 5 V part has an internal POR trip level of 4.5 V,
which means that there are no usable PSM levels on the 5 V
part. The 3 V part has a POR trip level of 2.45 V, allowing all
PSM trip points to be used.
PSMCON
SFR Address
Power-On Default
Bit Addressable
DD
comparator.
Power Supply Monitor
Control Register
DFH
DEH
No