ADUC816 Analog Devices, ADUC816 Datasheet - Page 39

• Manufacturer Part Number: ADUC816
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + Dual 16-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC816

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

REV. A
Serial Safe Mode
This mode disables serial download capability on the device. If
Serial Safe mode is activated and an attempt is made to reset
the part into serial download mode, i.e., RESET asserted and
deasserted with PSEN low, the part will interpret the serial
download reset as a normal reset only. It will, therefore, not
enter serial download mode but only execute a normal reset
sequence. Serial Safe mode can only be disabled by initiating a
code-erase command in parallel programming mode.
Using the Flash/EE Data Memory
The user Flash/EE data memory array consists of 640 bytes that
are configured into 160 (00H to 9FH) 4-byte pages as shown in
Figure 29.
As with other ADuC816 user-peripheral circuits, the interface to
this memory space is via a group of registers mapped in the SFR
space. A group of four data registers (EDATA1–4) are used to
hold 4-byte page data just accessed. EADRL is used to hold the
8-bit address of the page to be accessed. Finally, ECON is an 8-
bit control register that may be written with one of five Flash/EE
memory access commands to trigger various read, write, erase, and
verify functions. These registers can be summarized as follows:
ECON:
EADRL:
EDATA 1–4:
A block diagram of the SFR interface to the Flash/EE Data
Memory array is shown in Figure 30.
9FH
00H
SFR Address:
Function:
Default:
SFR Address:
Function:
Default:
SFR Address:
Function:
Default :
BYTE 1
BYTE 1
BYTE 2
BYTE 2
B9H
Controls access to 640 Bytes
Flash/EE Data Space.
00H
C6H
Holds the Flash/EE Data Page
Address. (640 Bytes => 160 Page
Addresses.)
00H
BCH to BFH respectively
Holds Flash/EE Data memory
page write or page read data bytes.
EDATA1–2 –> 00H
EDATA3–4 –> 00H
BYTE 3
BYTE 3
BYTE 4
BYTE 4
ECON—Flash/EE Memory Control SFR
This SFR acts as a command interpreter and may be written with
one of five command modes to enable various read, program and
erase cycles as detailed in Table XIII:
Command
Byte
01H
02H
03H
04H
05H
06H
07H to FFH
FUNCTION:
RECEIVES COMMAND DATA
Table XIII. ECON–Flash/EE Memory Control Register
Command Modes
FUNCTION:
EADRL
HOLDS THE 8-BIT PAGE
ADDRESS POINTER
9FH
00H
Command Mode
READ COMMAND.
Results in four bytes being read into EDATA1–4
from memory page address contained in EADRL.
PROGRAM COMMAND.
Results in four bytes (EDATA1–4) being written
to memory page address in EADRL. This write
command assumes the designated “write” page has
been pre-erased.
RESERVED FOR INTERNAL USE.
03H should not be written to the ECON SFR.
VERIFY COMMAND.
Allows the user to verify if data in EDATA1–4 is
contained in page address designated by EADRL.
A subsequent read of the ECON SFR will result
in a “zero” being read if the verification is valid,
a nonzero value will be read to indicate an invalid
verification.
ERASE COMMAND.
Results in an erase of the 4-byte page designated
in EADRL.
ERASE-ALL COMMAND.
Results in erase of the full Flash/EE Data memory
160-page (640 bytes) array.
RESERVED COMMANDS.
Commands reserved for future use.
BYTE 1 BYTE 2 BYTE 3 BYTE 4
BYTE 1 BYTE 2 BYTE 3 BYTE 4
INTERPRETER LOGIC
ECON COMMAND
ECON
FUNCTION:
HOLDS THE 4-BYTE
PAGE DATA
FUNCTION:
INTERPRETS THE FLASH
COMMAND WORD
EDATA1 (BYTE 1)
EDATA3 (BYTE 3)
EDATA4 (BYTE 4)
EDATA2 (BYTE 2)