LPC1112FDH28 NXP Semiconductors, LPC1112FDH28 Datasheet - Page 29

• Manufacturer Part Number: LPC1112FDH28
• Description: The LPC1112FDH28 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 10.
[1]
[2]
[3]
[4]
[5]
[6]
LPC111X
Product data sheet
Symbol
PIO1_7/TXD/
CT32B0_MAT1
PIO1_8/
CT16B1_CAP0
PIO1_9/
CT16B1_MAT0
PIO1_10/AD6/
CT16B1_MAT1
PIO1_11/AD7
PIO2_0
PIO2_0/DTR
PIO3_0 to PIO3_5
PIO3_2
PIO3_4
PIO3_5
V
XTALIN
XTALOUT
V
DD
SS
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to 2.6 V for
LPC111x/101/201/301, pins pulled up to full V
enabled.
See
reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down
mode.
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see
I
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
2
C-bus pads compliant with the I
Figure 46
LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package)
for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
Pin
32
7
12
20
27
1
28
13
14
6; 29 -
4
5
33
[3]
[3]
[6]
[6]
[3]
[3]
[5]
[5]
[3]
[3]
[3]
Start
logic
input
no
no
no
no
no
no
no
no
no
-
-
-
2
C-bus specification for I
Type Reset
I/O
O
O
I/O
I
I/O
O
I/O
I
O
I/O
I
I/O
O
I/O
I/O
I/O
I
I
O
-
All information provided in this document is subject to legal disclaimers.
DD
state
[1]
I;PU
-
-
I;PU
-
I;PU
-
I;PU
-
-
I;PU
-
I;PU
-
I;PU
I;PU
I;PU
-
-
-
-
level on LPC111x/002/102/202/302 (V
Rev. 7 — 1 March 2012
Description
PIO1_7 — General purpose digital input/output pin.
TXD — Transmitter output for UART.
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_8 — General purpose digital input/output pin.
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
PIO1_9 — General purpose digital input/output pin.
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
PIO1_10 — General purpose digital input/output pin.
AD6 — A/D converter, input 6.
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11 — General purpose digital input/output pin.
AD7 — A/D converter, input 7.
Port 2 — Port 2 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 2 pins depends on
the function selected through the IOCONFIG register block. Pins
PIO2_1 to PIO2_11 are not available.
PIO2_0 — General purpose digital input/output pin.
DTR — Data Terminal Ready output for UART.
Port 3 — Port 3 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 3 pins depends on
the function selected through the IOCONFIG register block. Pins
PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are not available.
PIO3_2 — General purpose digital input/output pin.
PIO3_4 — General purpose digital input/output pin.
PIO3_5 — General purpose digital input/output pin.
3.3 V supply voltage to the internal regulator, the external rail, and the
ADC. Also used as the ADC reference voltage.
Input to the oscillator circuit and internal clock generator circuits. Input
voltage must not exceed 1.8 V.
Output from the oscillator amplifier.
Thermal pad. Connect to ground.
2
C standard mode and I
LPC1110/11/12/13/14/15
2
C Fast-mode Plus.
32-bit ARM Cortex-M0 microcontroller
DD
= 3.3 V)); IA = inactive, no pull-up/down
Figure
© NXP B.V. 2012. All rights reserved.
45).
…continued
Figure
29 of 103
45).