LPC12D27FBD100 NXP Semiconductors, LPC12D27FBD100 Datasheet - Page 14

• Manufacturer Part Number: LPC12D27FBD100
• Description: The LPC12D27FBD100 is a ARM Cortex-M0 based microcontroller for embedded applications featuring a high level of integration and low power consumption
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 3.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
7. Functional description
LPC12D27
Product data sheet
Symbol
BP1
BP2
BP3
LCD_SDA
LCD_SCL
SYNC
CLK
V
V
V
DD
SS(LCD)
LCD
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled.
Digital I/O pin; default: pull-up enabled, no hysteresis.
I
Digital I/O pin with RESET function; default: pull-up enabled, no hysteresis.
Digital I/O pin with analog function; default: pull-up enabled, no hysteresis.
Digital I/O pin with analog function and WAKEUP function; default: pull-up enabled, no hysteresis.
High-drive digital I/O pin; default: pull-up enabled, no hysteresis.
See
2
C-bus pins; 5 V tolerant; open-drain; default: no pull-up/pull-down, no hysteresis.
Section
LPC12D27 LQFP100 pin description
7.2.3.
7.2.1 General description
7.1 LPC1227 microcontroller
7.2 LCD driver
See the LPC122x data sheet for a detailed functional description of the LPC1227
microcontroller.
See the PCF8576 data sheet for a detailed functional description of the PCF8576D LCD
driver.
The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily
cascaded for larger LCD applications. The PCF8576D communicates via the two-line
bidirectional I
auto-incremented addressing, by hardware subaddressing and by display memory
switching (static and duplex drive modes). Please refer to PCF8576D data sheet for
electrical data.
Pin
44
43
45
35
36
37
38
39
40
41
Start
logic
input
-
-
-
-
-
-
-
-
-
-
2
C-bus. Communication overheads are minimized by a display RAM with
Reset
state
[1]
V
V
V
[8]
[8]
[8]
[8]
-
-
-
All information provided in this document is subject to legal disclaimers.
LCD
LCD
LCD
[8]
[8]
[8]
Rev. 1 — 20 September 2011
Type
O
O
O
I/O
I/O
I/O
I/O
-
-
-
…continued
Description
LCD backplane output.
LCD backplane output.
LCD backplane output.
I
I
Cascade synchronization input/output.
External clock input/output.
1.8 V to 5.5 V power supply: Power supply voltage for the
PCF8576D.
LCD ground.
LCD power supply: LCD voltage.
2
2
C-bus serial data input/output.
C-bus serial clock input.
32-bit ARM Cortex-M0 microcontroller
LPC12D27
© NXP B.V. 2011. All rights reserved.
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