LPC2157_2158 NXP Semiconductors, LPC2157_2158 Datasheet - Page 20

• Manufacturer Part Number: LPC2157_2158
• Description: The LPC2157/2158 is a multi-chip module consisting of a LPC2138/2148 single-chipmicrocontroller combined with a PCF8576D Universal LCD driver in a low-cost 100-pinpackage
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2157_2158_2
Product data sheet
6.12.1 Features
6.13.1 Features
6.12 I
6.13 SPI serial I/O controller
6.14 SSP serial I/O controller
The LPC2157/2158 each contain two I
The I
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory)). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The I
I
The LPC2157/2158 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
The LPC2157/2158 each contain one Serial Synchronous Port controller (SSP). The SSP
controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact
with multiple masters and slaves on the bus. However, only a single master and a single
2
2
C-bus).
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C-bus serial I/O controller
Compliant with standard I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
Compliant with SPI specification.
Synchronous, Serial, Full Duplex, Communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
2
2
C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
C-bus implemented in LPC2157/2158 supports bit rates up to 400 kbit/s (Fast
2
C-bus can be used for test and diagnostic purposes.
Rev. 02 — 9 February 2009
2
C-bus interface.
2
C-bus controllers.
Single-chip 16-bit/32-bit microcontrollers
2
C-bus is a multi-master bus, it can be
LPC2157/2158
© NXP B.V. 2009. All rights reserved.
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