LPC2470 NXP Semiconductors, LPC2470 Datasheet - Page 24

• Manufacturer Part Number: LPC2470
• Description: NXP Semiconductors designed the LPC2470 microcontroller, powered by theARM7TDMI-S core, to be a highly integrated microcontroller for a wide range ofapplications that require advanced communications and high quality graphic displays
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 4.
LPC2470
Product data sheet
Symbol
DBGEN
TDO
TDI
TMS
TRST
TCK
RTCK
RSTOUT
RESET
XTAL1
XTAL2
RTCX1
RTCX2
V
V
V
V
n.c.
V
V
SSIO
SSCORE
SSA
DD(3V3)
DD(DCDC)(3V3)
DDA
Pin description
Pin
9
2
4
6
8
10
206
29
35
44
46
34
36
33, 63,
77, 93,
114,
133,
148,
169,
189,
200
32, 84,
172
22
15, 60,
71, 89,
112,
125,
146,
165,
181,
198
30, 117,
141
26, 86,
174
20
[1][16]
[1][17]
[1][16]
[1][16]
[1][16]
[1][17]
[12]
[13][14]
[13][14]
[13][15]
[13][15]
[13]
[13]
[1][16]
[13]
[13]
[13]
[13]
[13]
…continued
Ball
F4
D3
C2
E3
D1
E2
C3
K3
M2
M4
N4
K2
L2
L3, T5,
R9, P12,
N16,
H14,
E15,
A12, B6,
A2
K4, P10,
D12
J2
G3, P6,
P8, U13,
P17,
K16,
C17,
B13, C9,
D7
G14
H4, P11,
D11
G4
J4, L14,
[13]
[13][15]
[1][16]
[1][16]
[1][17]
[13][15]
[13]
[1][17]
[1][16]
[1][16]
[1][16]
[13][14]
[13]
[13]
[12]
[13][14]
[13]
[13]
[13]
All information provided in this document is subject to legal disclaimers.
Type
I
O
I
I
I
I
I/O
O
I
I
O
I
O
I
I
I
I
I
I
I
Rev. 4 — 8 September 2011
Description
DBGEN — JTAG interface control signal. Also used for boundary
scanning.
TDO — Test Data Out for JTAG interface.
TDI — Test Data In for JTAG interface.
TMS — Test Mode Select for JTAG interface.
TRST — Test Reset for JTAG interface.
TCK — Test Clock for JTAG interface. This clock must be slower than
of the CPU clock (CCLK) for the JTAG interface to operate.
RTCK — JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0])
to operate as Trace port after reset.
RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2470
being in Reset state.
external reset input: A LOW on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
ground: 0 V reference for the digital IO pins.
ground: 0 V reference for the core.
analog ground: 0 V reference. This should nominally be the same
voltage as V
error.
3.3 V supply voltage: This is the power supply voltage for the I/O ports.
not connected pins: These pins must be left unconnected (floating).
3.3 V DC-to-DC converter supply voltage: This is the power supply for
the on-chip DC-to-DC converter.
analog 3.3 V pad supply voltage: This should be nominally the same
voltage as V
This voltage is used to power the ADC and DAC.
SSIO
DD(3V3)
/V
SSCORE
but should be isolated to minimize noise and error.
, but should be isolated to minimize noise and
Flashless 16-bit/32-bit microcontroller
LPC2470
© NXP B.V. 2011. All rights reserved.
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