LPC3180 NXP Semiconductors, LPC3180 Datasheet - Page 19

• Manufacturer Part Number: LPC3180
• Description: The LPC3180 is an ARM9-based microcontroller for embedded applications requiringhigh performance combined with low power dissipation
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3180_2
Preliminary data sheet
6.12.1.1 Features
6.12.2.1 Features
6.12.1 USB device controller
6.12.2 USB host controller
6.12 USB interface
The LPC3180 supports USB in either device, host, or OTG configuration.
The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of register interface, serial interface engine, endpoint buffer memory and DMA
controller. The serial interface engine decodes the USB data stream and writes data to the
appropriate end point buffer memory. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. The
DMA controller when enabled transfers data between the endpoint buffer and the USB
RAM.
The host controller enables data exchange with various USB devices attached to the bus.
It consists of register interface, serial interface engine and DMA controller. The register
interface complies to the OHCI specification.
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Uses 32 kHz RTC clock
Fully compliant with USB 2.0 full-speed specification.
Supports 32 physical (16 logical) endpoints.
Supports control, bulk, interrupt and isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time.
RAM message buffer size based on endpoint realization and maximum packet size.
Supports bus-powered capability with low suspend current.
Supports DMA transfer on all non-control endpoints.
One duplex DMA channel serves all endpoints.
Allows dynamic switching between CPU controlled and DMA modes.
Double buffer implementation for bulk and isochronous endpoints.
OHCI compliant.
OHCI specifies the operation and interface of the USB host controller and SW driver.
The host controller has four USB states visible to the SW driver:
– USBOperational: Process lists and generate SOF tokens.
– USBReset: Forces reset signaling on the bus, SOF disabled.
– USBSuspend: Monitor USB for wake-up activity.
– USBResume: Forces resume signaling on the bus.
HCCA register points to interrupt and isochronous descriptors list.
ControlHeadED and BulkHeadED registers point to control and bulk descriptors list.
Rev. 02 — 15 February 2007
16/32-bit ARM microcontroller with external memory interface
LPC3180
© NXP B.V. 2007. All rights reserved.
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