LPC3180 NXP Semiconductors, LPC3180 Datasheet - Page 26

• Manufacturer Part Number: LPC3180
• Description: The LPC3180 is an ARM9-based microcontroller for embedded applications requiringhigh performance combined with low power dissipation
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3180_2
Preliminary data sheet
6.24.3 Power control and modes
6.24.4 APB bus
6.24.5 FAB bus
6.25.1 EmbeddedICE
6.25 Emulation and debugging
At the PLL output, there is a post-divider that can be used to bring the CCO frequency
down to the desired PLL output frequency. The post-divider value ‘P’, can divide the CCO
output by 1, 2, 4, 8, or 16. The post-divider can also be bypassed, allowing the PLL CCO
output to be used directly. The maximum PLL output frequency that is supported by the
CPU is 208 MHz.
The LPC3180 supports three operational modes, two of which are specifically designed to
reduce power consumption. The modes are: Run mode, Direct Run mode, and Stop
mode.
Run mode is the normal operating mode for applications that require the CPU, AHB bus,
or any peripheral function other than the USB block to run faster than the main oscillator
frequency. In Run mode, the CPU can run at up to 208 MHz and the AHB bus can run at
up to 104 MHz.
Direct Run mode allows reducing the CPU and AHB bus rates in order to save power.
Direct Run mode can also be the normal operating mode for applications that do not
require the CPU, AHB bus, or any peripheral function other than the USB block to run
faster than the main oscillator frequency. Direct Run mode is the default mode following
chip reset.
Stop mode causes all CPU and AHB operation to cease, and stops clocks to peripherals
other than the USB block.
Many peripheral functions are accessed by on-chip APB busses that are attached to the
higher speed AHB bus. The APB bus performs reads and writes to peripheral registers in
three peripheral clocks.
Some peripherals are placed on a special bus called FAB that allows faster CPU access
to those peripheral functions. Write access to FAB peripherals takes a single AHB clock.
Read access to FAB peripherals takes two AHB clocks.
The LPC3180 supports emulation and debugging via a dedicated JTAG serial port. An
Embedded Trace Buffer allows tracing program execution. The dedicated JTAG port
allows debugging of all chip features without impact to any pins that may be used in the
application.
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the
Remote Debug Protocol commands to the JTAG data needed to access the ARM core.
Rev. 02 — 15 February 2007
16/32-bit ARM microcontroller with external memory interface
LPC3180
© NXP B.V. 2007. All rights reserved.
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