P89LPC92X1 NXP Semiconductors, P89LPC92X1 Datasheet - Page 39

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P89LPC92X1

Manufacturer Part Number
P89LPC92X1
Description
The P89LPC9201/9211/922A1/9241/9251 is a single-chip microcontroller, available in lowcost packages, based on a high performance processor architecture that executesinstructions in two to four clocks, six times the rate of standard 80C51 devices
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
P89LPC92X1
Product data sheet
7.22.10 The 9
7.22.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
7.23 I
Unlike the conventional UART, in double buffering mode, the TI interrupt is generated
when the double buffer is ready to receive new data.
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TI interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will
be double-buffered together with SBUF data.
The I
connected to the bus, and it has the following features:
A typical I
P89LPC9201/9211/922A1/9241/9251 device provides a byte-oriented I
that supports data transfers up to 400 kHz.
2
Fig 11. I
C-bus serial interface
Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I
2
C-bus uses two wires (SDA and SCL) to transfer information between devices
th
bit (bit 8) in double buffering (modes 1, 2 and 3)
2
2
2
C-bus may be used for test and diagnostic purposes.
C-bus configuration is shown in
C-bus configuration
I
2
C-bus
All information provided in this document is subject to legal disclaimers.
P1.3/SDA
P89LPC9201/9211/
Rev. 2 — 1 December 2010
922A1/9241/9251
P89LPC9201/9211/922A1/9241/
P1.2/SCL
OTHER DEVICE
WITH I
R P
Figure
INTERFACE
2
C-BUS
11. The
R P
8-bit microcontroller with 8-bit ADC
OTHER DEVICE
WITH I
INTERFACE
2
C-BUS
002aae430
2
© NXP B.V. 2010. All rights reserved.
C-bus interface
SDA
SCL
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