P89LPC932A1 NXP Semiconductors, P89LPC932A1 Datasheet - Page 35
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
P89LPC932A1
Manufacturer Part Number
P89LPC932A1
Description
The P89LPC932A1 is a single-chip microcontroller, available in low cost packages, basedon a high performance processor architecture that executes instructions in two to fourclocks, six times the rate of standard 80C51 devices
Manufacturer
NXP Semiconductors
Datasheet
1.P89LPC932A1.pdf
(64 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P89LPC932A1
Manufacturer:
PHAEDRUS
Quantity:
185
Part Number:
P89LPC932A1FA
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
P89LPC932A1FA,112
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
P89LPC932A1FA,129
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
P89LPC932A1FAЈ¬112
Manufacturer:
NXP
Quantity:
9 947
Company:
Part Number:
P89LPC932A1FDH
Manufacturer:
VISHAY
Quantity:
120 000
Part Number:
P89LPC932A1FDH
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
P89LPC932A1FDHЈ¬512
Manufacturer:
NXP
Quantity:
836
Company:
Part Number:
P89LPC932A1FHN
Manufacturer:
IR
Quantity:
4 510
NXP Semiconductors
P89LPC932A1_3
Product data sheet
Fig 16. SPI block diagram
SPI STATUS REGISTER
BY 4, 16, 64, 128
CPU clock
DIVIDER
SELECT
SPI CONTROL
7.22 Serial Peripheral Interface (SPI)
The P89LPC932A1 provides another high-speed serial communication interface—the SPI
interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in
Master mode or up to 2 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write
Collision Flag Protection.
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
Typical connections are shown in
•
•
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device
uses its SS pin to determine whether it is selected.
interrupt
request
SPI clock (master)
SPI
MSTR
SPEN
Rev. 03 — 12 March 2007
internal
data
bus
8-bit microcontroller with accelerated two-clock 80C51 core
SPI CONTROL REGISTER
8-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK LOGIC
Figure 17
clock
through
Figure
P89LPC932A1
19.
M
M
M
S
S
S
CONTROL
LOGIC
PIN
© NXP B.V. 2007. All rights reserved.
002aaa900
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
SS
P2.4
35 of 64