ST72561R9 STMicroelectronics, ST72561R9 Datasheet - Page 186

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ST72561R9

Manufacturer Part Number
ST72561R9
Description
8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72561R9

Hdflash Endurance
100 cycles, data retention 40 years at 85°C
5 Power Saving Modes
Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow
ST72561
beCAN CONTROLLER (Cont’d)
– The FIFO interrupt can be generated by the fol-
– The transmit, error and status change inter-
186/265
lowing events:
rupt can be generated by the following events:
– Reception of a new message, FMP bits in the
– FIFO0 full condition, FULL bit in the CRFR0
– FIFO0 overrun condition, FOVR bit in the
– Transmit mailbox 0 becomes empty, RQCP0
– Transmit mailbox 1 becomes empty, RQCP1
– Error condition, for more details on error con-
– Wake-up condition, SOF monitored on the
CRFR0 register incremented.
register set.
CRFR0 register set.
bit in the CTSR register set.
bit in the CTSR register set.
ditions please refer to the CAN Error Status
register (CESR).
10.9.6 Register Access Protection
Erroneous access to certain configuration regis-
ters can cause the hardware to temporarily disturb
the whole CAN network. Therefore the following
registers can be modified by software only while
the hardware is in initialization mode:
CBTR0, CBTR1, CFCR0, CFCR1, CFMR and
CDGR registers.
Although the transmission of incorrect data will not
cause problems at the CAN network level, it can
severely disturb the application. A transmit mail-
box can be only modified by software while it is in
empty state (refer to
States).
The filters must be deactivated before their value
can be modified by software. The modification of
the filter configuration (scale or mode) can be
done by software only in initialization mode.
CAN Rx signal.
Figure 7. Transmit Mailbox

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