ST72561R9 STMicroelectronics, ST72561R9 Datasheet - Page 187

• Manufacturer Part Number: ST72561R9
• Description: 8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
• Manufacturer: STMicroelectronics

Specifications of ST72561R9

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

beCAN CONTROLLER (Cont’d)
10.9.7 BeCAN Cell Limitations
10.9.7.1 FIFO Corruption
FIFO corruption occurs in the following case:
WHEN the beCAN RX FIFO already holds two
messages (that is, FMP == 2)
WHILE the beCAN requests the transfer of a new
receive message into the FIFO (this lasts one CPU
cycle)
Figure 109. FIFO Corruption
and Receive Message D
Release Message C
Receive Message A
Receive Message B
Receive Message C
Release Message A
Release Message B
Receive Message E
Release Message E
Release Message B
AND the application releases the FIFO (with
the instruction CRFR = B_RFOM;)
THEN the internal FIFO pointer is not updat-
ed
BUT the FMP bits are updated correctly
* pointer to next receive location
v pointer to next message to be released
Initial State
FMP
0
1
2
3
2
2
3
2
1
0
v
E B C
v
v
v
A B C
E B C
E B C
* v
- - -
A - -
A B -
A B C
D B C
D B C
E B C
*
FIFO
*
*
v
* v
*
*
* v
v
*
*
*
v
v
When the FIFO is empty, v and * point to the same location
E released instead of B
* does not move because FIFO is full (normal operation)
D is overwritten by E
C released
* and v are not pointing to the same message
the FIFO is empty
* Does not move, pointer corruption
Normal operation
As the FIFO pointer is not updated correctly, this
causes the last message received to be overwrit-
ten by any incoming message. This means one
message is lost as shown in the example in
16. The beCAN will not recover normal operation
until a device reset occurs.
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Figure