ST7LITEU09 STMicroelectronics, ST7LITEU09 Datasheet - Page 38

• Manufacturer Part Number: ST7LITEU09
• Description: ST7ULTRALITE - 8-BIT MCU WITH 2K SINGLE VOLTAGE FLASH MEMORY, ADC, TIMERS
• Manufacturer: STMicroelectronics

Specifications of ST7LITEU09

• 2k Bytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• 128 Bytes Data Eeprom. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• Clock Sources: internal trimmable 8MHz RC oscillator, internal low power, low frequency RC oscillator or external clock
• Five Power Saving Modes: Halt, Auto Wake Up from Halt, Active-Halt, Wait and Slow
• One 8-bit Lite Timer (lt) With Prescaler Including: watchdog, 1 realtime base and 1 input capture

Supply, reset and clock management
7.4
7.4.1
Note:
Caution:
38/139
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three Reset sources as shown in
●
●
●
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
These sources act on the RESET pin and it is always kept low during the delay phase.
The Reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic Reset sequence consists of 3 phases as shown in
●
●
●
When the ST7 is unprogrammed or fully erased, the Flash is blank and the Reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 512 CPU clock cycle delay allows the oscillator to stabilise and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay is
automatically selected depending on the clock source chosen by option byte after a reset or
depending on the clock source selected before entering Halt mode or AWU from Halt mode.
Refer to
The Reset vector fetch phase duration is 2 clock cycles.
Table 8.
Figure 15. Reset sequence phases
External RESET source pulse
Internal LVD Reset (low voltage detection)
Internal WATCHDOG Reset
Active phase depending on the Reset source
256 or 512 CPU clock cycle delay (see table below)
Reset vector fetch
Figure
Table
CPU clock cycle delay
8.
External clock (connected to CLKIN pin)
16.
Internal RC oscillator
Clock source
AWURC
Active Phase
256 OR 512 CLOCK CYCLES
INTERNAL RESET
RESET
VECTOR
FETCH
Figure
ST7LITEU05 ST7LITEU09
15:
CPU clock cycle delay
Figure
512
256
16: