ST7LITEU09 STMicroelectronics, ST7LITEU09 Datasheet - Page 78

• Manufacturer Part Number: ST7LITEU09
• Description: ST7ULTRALITE - 8-BIT MCU WITH 2K SINGLE VOLTAGE FLASH MEMORY, ADC, TIMERS
• Manufacturer: STMicroelectronics

Specifications of ST7LITEU09

• 2k Bytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• 128 Bytes Data Eeprom. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• Clock Sources: internal trimmable 8MHz RC oscillator, internal low power, low frequency RC oscillator or external clock
• Five Power Saving Modes: Halt, Auto Wake Up from Halt, Active-Halt, Wait and Slow
• One 8-bit Lite Timer (lt) With Prescaler Including: watchdog, 1 realtime base and 1 input capture

On-chip peripherals
Caution:
78/139
Bit 2 = OVF Overflow flag.
When set, the OVF bit stays high for 1 f
selection) after it has been cleared by software.
Bit 1 = OVFIE Overflow interrupt enable.
Bit 0 = CMPIE Compare interrupt enable.
Counter register high (CNTRH)
Reset Value: 0000 0000 (00h)
Counter register low (CNTRL)
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved, must be kept cleared.
Bits 11:0 = CNTR[11:0] Counter Value.
CN7
15
This bit is set by hardware and cleared by software by reading the ATCSR register. It
indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
This bit is read/write by software and clear by hardware after a reset. It allows to mask
the interrupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
This 12-bit register is read by software and cleared by hardware after a reset. The
counter is incremented continuously as soon as a counter clock is selected. To obtain
the 12-bit value, software should read the counter value in two consecutive read
operations. As there is no latch, it is recommended to read LSB first. In this case,
CNTRH can be incremented between the two read operations and to have an accurate
result when f
are read.
When a counter overflow occurs, the counter restarts from the value specified in the
ATR register.
0
7
CN6
0
timer
= f
CPU
CN5
0
, special care must be taken when CNTRL values close to FFh
CN4
COUNTER
0
Read only
Read only
cycle (up to 1ms depending on the clock
CN11
CN3
CN10
CN2
ST7LITEU05 ST7LITEU09
CN9
CN1
CN8
CN0
8
0