ST7LITEU09 STMicroelectronics, ST7LITEU09 Datasheet - Page 39

• Manufacturer Part Number: ST7LITEU09
• Description: ST7ULTRALITE - 8-BIT MCU WITH 2K SINGLE VOLTAGE FLASH MEMORY, ADC, TIMERS
• Manufacturer: STMicroelectronics

Specifications of ST7LITEU09

• 2k Bytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• 128 Bytes Data Eeprom. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• Clock Sources: internal trimmable 8MHz RC oscillator, internal low power, low frequency RC oscillator or external clock
• Five Power Saving Modes: Halt, Auto Wake Up from Halt, Active-Halt, Wait and Slow
• One 8-bit Lite Timer (lt) With Prescaler Including: watchdog, 1 realtime base and 1 input capture

ST7LITEU05 ST7LITEU09
7.4.2
7.4.3
7.4.4
Figure 16. Reset block diagram
1. See “Illegal opcode reset” on page 92. for more details on illegal opcode reset conditions.
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Electrical Characteristic
section for more details.
A Reset signal originating from an external source must have a duration of at least t
in order to be recognized (see
MCU can enter reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V
the minimum level specified for the selected f
A proper reset signal for a slow rising V
RC network connected to the RESET pin.
Internal low voltage detector (LVD) reset
Two different Reset sequences caused by the internal LVD circuitry can be distinguished:
●
●
The device RESET pin acts as an output that is pulled low when V
V
The LVD filters spikes on V
DD
<V
Power-on reset
Voltage drop reset
IT-
RESET
(falling edge) as shown in
V
DD
DD
R
ON
larger than t
Figure
Figure
FILTER
17). This detection is asynchronous and therefore the
DD
g(VDD)
supply can generally be provided by an external
17.
CLKIN
GENERATOR
PULSE
to avoid parasitic resets.
frequency.
Supply, reset and clock management
ILLEGAL OPCODE RESET
WATCHDOG RESET
LVD RESET
DD
<V
IT+
INTERNAL
RESET
ON
(rising edge) or
weak pull-up
DD
h(RSTL)in
is over
1)
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