ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 68
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ST72324BK2
Manufacturer Part Number
ST72324BK2
Description
5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72324BJ6.pdf
(193 pages)
Specifications of ST72324BK2
Hdflash Endurance
1 kcycle at 55 °C, data retention 40 years at 85 °C
Clock Sources
crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
4 Power Saving Modes
Slow, Wait, Active-halt, and Halt
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On-chip peripherals
10.1.5
10.1.6
10.1.7
10.1.8
68/193
Low power modes
Table 34.
Hardware Watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the option byte description in
Flash
Using Halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled:
Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected
WDG reset immediately after waking up the microcontroller.
Interrupts
None.
Mode
Slow
Wait
Halt
devices.
No effect on Watchdog
MCCSR register
OIE bit in
Effect of lower power modes on Watchdog
0
0
1
WDGHALT bit in
option byte
0
1
x
No Watchdog reset is generated. The MCU enters
Halt mode. The Watchdog counter is decremented
once and then stops counting and is no longer able to
generate a watchdog reset until the MCU receives an
external interrupt or a reset.
If an external interrupt is received, the Watchdog
restarts counting after 256 or 4096 CPU clocks. If a
reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by
option byte. For application recommendations, see
Section 10.1.7
A reset is generated.
No reset is generated. The MCU enters Active-halt
mode. The Watchdog counter is not decremented. It
stop counting. When the MCU receives an oscillator
interrupt or external interrupt, the Watchdog restarts
counting immediately. When the MCU receives a
reset the Watchdog restarts counting after 256 or
4096 CPU clocks.
Description
below.
Section 14.1:
ST72324Bxx
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