ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 91

• Manufacturer Part Number: ST72324BK2
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BK2

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

ST72324Bxx
Table 50.
Control/Status Register (CSR)
Table 51.
CSR
Bit
3:2 CC[1:0]
Bit Name
M
7
5
4
1
0
ICF1
RO
7
EXEDG
ICF1
IEDG2
Name
PWM
OPM
Input capture flag 1
CR2 register description (continued)
CSR register description
OCF1
One Pulse mode
Pulse width modulation
Clock control
Input edge 2
External clock edge
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.
RO
0: One Pulse mode is not active.
1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the
OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the
generated pulse depends on the contents of the OC1R register.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the
length of the pulse depends on the value of OC1R register; the period depends on
the value of OC2R register.
The timer clock mode depends on these bits.
00: Timer clock = f
01: Timer clock = f
10: Timer clock = f
11: Timer clock = external clock (where available)
Note: If the external clock pin is not available, programming the external clock
configuration stops the counter.
This bit determines which type of level transition on the ICAP2 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
This bit determines which type of level transition on the external clock pin EXTCLK
will trigger the counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
6
TOF
RO
5
CPU
CPU
CPU
/4
/2
/8
ICF2
RO
4
Function
Function
OCF2
RO
3
TIMD
R/W
2
Reset value: xxxx x0xx (xxh)
On-chip peripherals
1
Reserved
-
0
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