ST72124J2 STMicroelectronics, ST72124J2 Datasheet - Page 42

• Manufacturer Part Number: ST72124J2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72124J2

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes

ST72334J/N, ST72314J/N, ST72124J
I/O PORTS (Cont’d)
CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.
WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.
12.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.
Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.
Figure 27. Interrupt I/O Port State Transitions
The I/O port register configurations are summa-
rized as follows.
42/153
floating/pull-up
interrupt
INPUT
01
(reset state)
floating
INPUT
00
Figure 27
open-drain
OUTPUT
10
XX
Other transitions
= DDR, OR
OUTPUT
push-pull
11
Standard Ports
PA5:4, PC7:0, PD7:0, PE7:4, PE1:0, PF7:6, PF4
Interrupt Ports
PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)
PA3, PB4, PB3, PF2 (without pull-up)
True Open Drain Ports
PA7:6
floating input
pull-up input
open drain output
push-pull output
floating input
pull-up interrupt input
open drain output
push-pull output
floating input
floating interrupt input
open drain output
push-pull output
floating input
open drain (high sink ports)
MODE
MODE
MODE
MODE
DDR
DDR
DDR
0
0
1
1
0
0
1
1
0
0
1
1
DDR
OR
OR
OR
0
1
0
1
0
1
0
1
0
1
0
1
0
1