ST72124J2 STMicroelectronics, ST72124J2 Datasheet - Page 81
ST72124J2
Manufacturer Part Number
ST72124J2
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
Manufacturer
STMicroelectronics
Datasheet
1.ST72124J2.pdf
(153 pages)
Specifications of ST72124J2
Clock Sources
crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
4 Power Saving Modes
Halt, Active-Halt, Wait and Slow
Two 16-bit Timers With
2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.5 Low Power Modes
14.4.6 Interrupts
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
WAIT
HALT
SPI End of Transfer Event
Master Mode Fault Event
Mode
No effect on SPI.
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
Interrupt Event
Description
ST72334J/N, ST72314J/N, ST72124J
MODF
Event
SPIF
Flag
Control
Enable
SPIE
Bit
from
Wait
Exit
Yes
Yes
from
Exit
Halt
81/153
No
No
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