ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 150
ST72561J6-Auto
Manufacturer Part Number
ST72561J6-Auto
Description
8-bit MCU for automotive
Manufacturer
STMicroelectronics
Datasheet
1.ST72561R9-AUTO.pdf
(324 pages)
Specifications of ST72561J6-Auto
Hdflash Endurance
100 cycles, data retention 20 years at 55 °C
5 Power Saving Modes
halt, auto wake up from halt, active halt, wait and slow
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Serial peripheral interface (SPI)
Note:
14.5
14.5.1
150/324
MISO pin and the MOSI pin are directly connected between the master and the slave
device.
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Figure 74. Data clock timing diagram
Error flags
Master mode fault (MODF)
Master mode fault occurs when the master device’s SS pin is pulled low.
When a Master mode fault occurs:
●
●
●
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
The MSTR bit is reset, thus forcing the device into slave mode.
(from slave)
(from slave)
(to slave)
(to slave)
(from master)
(from master)
MISO
MOSI
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
MOSI
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
SS
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
MSBit
MSBit
MSBit
MSBit
Doc ID 12370 Rev 8
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
CPHA = 0
CPHA = 1
Bit 4
Bit 4
Bit 4
Bit 4
Bit3
Bit3
Bit3
Bit3
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
LSBit
LSBit
LSBit
LSBit
ST72561-Auto
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