ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 237

• Manufacturer Part Number: ST72561J6-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
critical period. But the application may lose additional time waiting in the while loop as we
are no longer able to guarantee a maximum of 6 CAN bit times spent in the workaround.
In this particular case the time the application can spend in the workaround may increase up
to a full CAN frame, depending of the frame contents. This case is very rare but happens
when a specific sequence is present on in the CAN frame.
The example in
8/f
If the application is using the maximum baud rate and the possible delay caused by the
workaround is not acceptable, there is another workaround which reduces the Rx pin
sampling time.
Workaround 2 (see
the FIFO can be released immediately. If yes, the program goes through a sequence of test
instructions on the RX pin that last longer than the time between the acknowledge dominant
bit and the critical time slot. If the Rx pin is in recessive state for more than 8 CAN bit times,
it means we are now after the acknowledge and the critical slot. If a dominant bit is read on
the bus, we can release the FIFO immediately. This workaround has to be written in
assembly language to avoid the compiler optimizing the test sequence.
The implementation shown here is for the CAN bus maximum speed (1 Mbaud @ 8 MHz
CPU clock).
Figure 113. Reception at maximum CAN baud rate
Figure 114. Workaround 2
Ld
And
Cp
Jrne
Btjf
Btjf
Btjf
Btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
btjf
_RELEASE:
bset
CPU
Sampling of Rx pin
and the sampling time is 10/f
CAN Bus signal
a, CRFR
a,#3
a,#2
_RELEASE
CMSR,#5,_RELEASE ; test if reception on going.
CDGR,#3,_RELEASE ; sample RX pin for 8 CAN bit time
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CDGR,#3,_RELEASE
CRFR,#5
Figure 113
Figure
R
R
114) first tests that FMP = 2 and the CAN cell is receiving, if not
shows reception at maximum CAN baud rate: In this case t
R
; test FMP=2 ?
; if not release
; if not release
Doc ID 12370 Rev 8
R
D
CPU
R
R
.
R
R
D
R
R
R
R
D
R
beCAN controller (beCAN)
R
R
R
D
R
R
R
R
D
237/324
CAN
is