ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 154

• Manufacturer Part Number: ST72561J6-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

Serial peripheral interface (SPI)
14.7
Note:
14.8
14.8.1
Note:
154/324
Interrupts
Table 57.
The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
Register description
Control register (SPICR)
Read/ write
Reset value: 0000 xxxx (0xh)
Bit 7 = SPIE Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also cleared by hardware when, in master mode,
SS = 0 (see
peripheral is not initially connected to the external pins.
Bit 5 = SPR2 Divider Enable
This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0]
bits to set the baud rate. Refer to
This bit has no effect in slave mode.
SPI End of Transfer Event
Master Mode Fault Event
Overrun Error
SPIE
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault
or Overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register)
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
0: Divider by 2 enabled
1: Divider by 2 disabled
7
Interrupt event
Master mode fault
SPI interrupt control and wake-up capability
SPE
SPR2
Doc ID 12370 Rev 8
(MODF)). The SPE bit is cleared by reset, so the SPI
Table
MODF
Event
SPIF
OVR
flag
MSTR
58.
CPOL
control
Enable
SPIE
bit
CPHA
from
wait
Exit
Yes
SPR1
ST72561-Auto
from
Exit
halt
Yes
No
SPR0
0