ST72361K6 STMicroelectronics, ST72361K6 Datasheet - Page 169

• Manufacturer Part Number: ST72361K6
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72361K6

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

10-BIT A/D CONVERTER (ADC) (Cont’d)
10.9.3.2 A/D Conversion
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the “I/O ports”
chapter. Using these pins as analog inputs does
not affect the ability of the port to be read as a logic
input.
In the ADCCSR register:
– Select the CS[3:0] bits to assign the analog
ADC Conversion mode
In the ADCCSR register:
– Set the ADON bit to enable the A/D converter
When a conversion is complete:
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll EOC bit
2. Read the ADCDRL register
3. Read the ADCDRH register. This clears EOC
To read only 8 bits, perform the following steps:
1. Poll EOC bit
2. Read the ADCDRH register. This clears EOC
10.9.3.3 Changing the conversion channel
The application can change channels during con-
version. When software modifies the CH[3:0] bits
channel to convert.
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
automatically.
automatically.
in the ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D con-
verter starts converting the newly selected chan-
nel.
10.9.3.4 ADCDR consistency
If an End Of Conversion event occurs after soft-
ware has read the ADCDRLSB but before it has
read the ADCDRMSB, there would be a risk that
the two values read would belong to different sam-
ples.
To guarantee consistency:
This is important, as the ADCDR register will not
be updated until the ADCDRH register is read.
10.9.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions.
10.9.5 Interrupts
None.
Mode
WAIT
HALT
– The ADCDRL and the ADCDRH registers are
– The ADCDRL and the ADCDRH registers are
locked when the ADCCRL is read
unlocked when the ADCDRH register is read
or when ADON is reset.
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
t
before accurate conversions can be
performed.
STAB
(see Electrical Characteristics)
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