ST72361K6 STMicroelectronics, ST72361K6 Datasheet - Page 96

• Manufacturer Part Number: ST72361K6
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72361K6

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

ST72361
8-BIT TIMER (Cont’d)
10.5.3.3 Output Compare
In this section, the index, i, may be 1 or 2 because
there are two output compare functions in the 8-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
Two 8-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC
Timing resolution is one count of the free running
counter: (f
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OCiE bit if an output is needed then the
– Select the timer clock (CC[1:0]) (see
And select the following in the CR1 register:
96/225
OCMPi pin is dedicated to the output compare i
signal.
Clock Control
– Assigns pins with a programmable value if the
– Sets a flag in the status register
– Generates an interrupt if enabled
OCiE bit is set
CPU
/
CC[1:0]
Bits).
i
R value to 00h.
).
Table 19
– Select the OLVLi bit to applied to the OCMPi pins
– Set the OCIE bit to generate an interrupt if it is
When a match is found between OCRi register
and CR register:
– OCFi bit is set.
– The OCMPi pin takes OLVLi bit value (OCMPi
– A timer interrupt is generated if the OCIE bit is
The OC
ing application can be calculated using the follow-
ing formula:
Where:
Δ
f
PRESC
Clearing the output compare interrupt request
(that is, clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is
2. An access (read or write) to the OCiR register.
CPU
t
after the match occurs.
needed.
pin latch is forced low during reset).
set in the CR1 register and the I bit is cleared in
the CC register (CC).
set.
i
R register value required for a specific tim-
= Output compare period (in seconds)
= PLL output x2 clock frequency in hertz
= Timer prescaler factor (2, 4, 8 or 8000
(or f
depending on CC[1:0] bits, see
19 Clock Control
Δ
OSC
OCiR =
/2 if PLL is not enabled)
Δt
PRESC
Bits)
*
f
CPU
Table