DS2460 Maxim, DS2460 Datasheet - Page 3

• Manufacturer Part Number: DS2460
• Description: The DS2460 SHA-1 Coprocessor with EEPROM is a hardware implementation of the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA computation required for authenticating SHA devices and fo
• Manufacturer: Maxim

Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a
STOP and START Condition
Capacitive Load for Each Bus
Line
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
PIN DESCRIPTION
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS2460. The DS2460 communicates with a host processor through its I²C bus interface in standard-mode or in
fast-mode. The logic state of three address pins determines the I²C slave address of the DS2460, allowing up to 8
devices to operate on the same bus segment without requiring a hub. For more information (including Figure 2)
refer to the full version of the data sheet.
PIN
1
2
3
4
5
6
7
8
PARAMETER
NAME
Specification at -40°C is guaranteed by design and characterization only and not production tested.
Write-cycle endurance is degraded as T
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T
Guaranteed by 100% production test at elevated temperature for a shorter amount of time;
equivalence of this production test to data sheet limit at operating temperature range is established by
reliability testing.
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term
storage at elevated temperatures is not recommended; the device can lose its write capability after 10
years at +125°C or 40 years at +85°C.
All values are referred to V
Applies to SDA, SCL, AD2, AD1, AD0.
Guaranteed by simulation only, not production tested.
I/O pins of the DS2460 do not obstruct the SDA and SCL lines if V
The DS2460 provides a hold time of at least 300ns for the SDA signal (referred to the V
signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
SCL signal.
A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement
t
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + t
standard-mode I²C-bus specification) before the SCL line is released.
C
to I²C-Bus Specification v2.1 are allowed.
SU:DAT
GND
SDA
AD0
AD1
AD2
SCL
V
NC
B
CC
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
 2 50ns must then be met. This is automatically the case if the device does not stretch the LOW
I²C Address Inputs; must be tied to VCC or GND. These inputs determine the I²C slave
address of the device, see Figure 5.
Ground Reference
Not Connected
I²C Serial Data Input/Output; must be tied to V
I²C Serial Clock Input; must be tied to V
Power Supply Input
HD:DAT
has only to be met if the device does not stretch the LOW period (t
SYMBOL
t
t
t
t
HD:DAT
SU:DAT
SU:STO
SU:STA
t
C
BUF
IHmin
B
and V
A
increases.
(Notes 11, 12)
(Note 13)
(Note 14)
ILmax
A
CONDITIONS
increases.
levels.
3 of 9
SU:DAT
FUNCTION
CC
through a pullup resistor.
= 1000 + 250 = 1250ns (according to the
CC
through a pullup resistor.
MIN
100
CC
0.6
0.6
1.3
is switched off.
TYP
MAX
400
0.9
IHmin
LOW
) of the
of the SCL
UNITS
µs
pF
µs
ns
µs
µs