DS2460 Maxim, DS2460 Datasheet - Page 5

• Manufacturer Part Number: DS2460
• Description: The DS2460 SHA-1 Coprocessor with EEPROM is a hardware implementation of the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA computation required for authenticating SHA devices and fo
• Manufacturer: Maxim

Slave Address
The slave address to which the DS2460 responds is shown in Figure 5. The logic states at the address pins AD0,
AD1 and AD2 determine the value of the address bits A0, A2, and A4. The address pins allow the device to
respond to one of eight possible slave addresses. The slave address is part of the slave-address/control byte. The
last bit of the slave-address/control byte (R/W) defines the data direction. When set to a 0, subsequent data will
flow from master to slave (write access mode); when set to a 1, data will flow from slave to master (read access
mode).
Figure 4. I²C Protocol Overview
Figure 5. DS2460 Slave Address
I²C Definitions
The following terminology is commonly used to describe I²C data transfers. The timing references are defined in
Figure 6.
Bus Idle or Not Busy
Both, SDA and SCL, are inactive and in their logic HIGH states.
START Condition
To initiate communication with a slave, the master has to generate a START condition. A START condition is
defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH. A valid slave address must be
sent by the master and acknowledged by the slave before subsequent START conditions are recognized.
STOP Condition
To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as
a change in state of SDA from LOW to HIGH while SCL remains HIGH. A valid slave address must be sent by the
master and acknowledged by the slave before subsequent STOP conditions are recognized.
SDA
SCL
Idle
Condition
START
MS-bit
1
Slave Address
Most Signi-
ficant Bit
2
A6
1
6
A5
0
7-Bit Slave Address
7
AD2
A4
R/ W
Acknowledgment
8
from Receiver
A3
AD2, AD1, AD0
0
5 of 9
ACK
ACK
Pin States
bit
9
AD1
A2
A1
0
1
Repeated if more bytes
AD0 R/W
2
A0
are transferred
Read or Write
Determines
8
ACK
ACK
bit
9
STOP Condition
Repeated START
Condition