73S1215F Maxim, 73S1215F Datasheet - Page 13

• Manufacturer Part Number: 73S1215F
• Description: The Teridian 73S1215F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

DS_1215F_003
Register
ERASE
PGADDR
FLSHCTL
Rev. 1.4
Address
0xB7
0xB2
0x94
SFR
R/W
R/W
R/W
R/W
W
W
Table 3: Flash Special Function Registers
This register is used to initiate either the Flash Mass Erase cycle or the
Flash Page Erase cycle. Specific patterns are expected for ERASE in
order to initiate the appropriate Erase cycle (default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write to
Any other pattern written to ERASE will have no effect.
Flash Page Erase Address register containing the flash memory page
address (page 0 through 127) that will be erased during the Page Erase
cycle (default = 0x00). Note: the page address is shifted left by one bit
(see detailed description above).
Must be re-written for each new Page Erase cycle.
Bit 0 (FLSH_PWE): Program Write Enable:
0 – MOVX commands refer to XRAM Space, normal operation (default).
1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to
this bit are inhibited when interrupts are enabled.
Bit 1 (FLSH_MEEN): Mass Erase Enable:
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Bit 6 (SECURE):
Enables security provisions that prevent external reading of flash memory
and CE program RAM. This bit is reset on chip reset and may only be
set. Attempts to write zero are ignored.
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write to
PGADDR @ SFR 0xB7.
FLSH_MEEN @ SFR 0xB2 and the debug port must be enabled.
Description
73S1215F Data Sheet
13