73S1215F Maxim, 73S1215F Datasheet - Page 33

• Manufacturer Part Number: 73S1215F
• Description: The Teridian 73S1215F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

DS_1215F_003
1.7.3
The 80515 core provides 10 interrupt sources with four priority levels. Each source has its own request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0,
IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.
IEN2. Some of the 10 sources are multiplexed in order to expand the number of interrupt sources.
These will be described in more detail in the respective sections.
These will be described in more detail in the respective sections.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of
the 73S1215F, for example the USB interface, USR I/O, RTC, smart card interface, analog comparators,
the 73S1215F, for example the USB interface, USR I/O, RTC, smart card interface, analog comparators,
etc. The external interrupt configuration is shown in
etc. The external interrupt configuration is shown in
Figure 8.
Figure 8.
Rev. 1.4
Interrupts
VCC_OK
Card_Det
USR2
USR5
USR6
USR0
USR1
USR3
USR4
USR7
Serial
Serial
KeyPad
INT3
Ch 0
Ch 1
INT2
Analog
Comp
USB
RTC
I
2
C
VccCTL
CRDCtl
Figure 8: External Interrupt Configuration
Pads
Pads
USR
INT
+
VDD_Fault
USR
Card Event
Ctl
Int
VCC_TMR
USR
Int
Ctl
USR
Int
Ctl
USR
Ctl
Int
Wait Timeout
TX_Event
TX_Error
RX_Error
Tx_Sent
RxData
INT5Ctl
INT6Ctl
PDMUXCtl
SCInt
+
During STOP, IDLE when
PWRDN bit is set
SCIE
Delay
1
0
+
t0
t1
int4
int5
int6
int0
int1
int2
int3
SerChan 0 int
SerChan 1 int
Clear PWRDN bit
CORE
MPU
73S1215F Data Sheet
IEN1
and
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