73S1215F Maxim, 73S1215F Datasheet - Page 82

• Manufacturer Part Number: 73S1215F
• Description: The Teridian 73S1215F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

1.7.15.4 Bypass Mode
It is possible to bypass the smart card UART in order for the firmware to support non-T=0/T=1 smart cards.
This is called Bypass mode. In this mode the embedded firmware will communicate directly with the
selected smart card and drive I/O during transmit and read I/O during receive in order to communicate with
the smart card. In this mode, ATR processing is under firmware control. The firmware must sequence the
interface signals as required. Firmware must perform TS processing, parity checking, break generation and
CRC/LRC calculation (if required).
1.7.15.5 Synchronous Operation Mode
The 73S1215F supports synchronous operation. When sync mode is selected for either interface, the CLK
signal is generated by the ETU counter. The values in FDReg, SCCLK, and
the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the interface must
be selected to obtain a smart card clock signal. In sync mode, input data is sampled on the rise of CLK,
and output data is changed on the fall of CLK.
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T = 1 Mode
ATR Timing Parameters
TRANSMISSION
BLOCK1
T = 0 Mode
IO
RLen(7:0)
RST
VCC_OK
CHAR 1
EGT
CHAR 1
Figure 20: Guard, Block, Wait and ATR Time Definitions
(By seting Last_TXByte and
TX/RXB=0 during CHAR N,
RX mode will start after last
TSTO(7:0)
CHAR 2
< WWT
> EGT
WWT is set by the value in the BWT registers.
TX byte)
CHAR N
IWT(15:0)
CHAR 1
> BWT
CHAR 2
ATRTO(15:0)
CHAR
CHAR 2
N+1
< CWT
RECEPTION
BLOCK2
CHAR
N+2
CHAR N
SCECLK
CHAR
N+3
BGT(4:0)
must be set to obtain
Rev. 1.4
TX