SAA7146AH/V4,557 NXP Semiconductors, SAA7146AH/V4,557 Datasheet - Page 109

• Manufacturer Part Number: SAA7146AH/V4,557
• Description: IC VIDEO SPCI BRIDGE HP 160-QFP
• Manufacturer: NXP Semiconductors
• Type: Video Bridger

Specifications of SAA7146AH/V4,557

• Package / Case: 160-QFP
• Applications: DTV
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1318; 935269343557; SAA7146AHBB

Philips Semiconductors
Table 100 Feedback buffers
Under control of the time slot list, a collected Dword is then stored into the input FIFO. The FIFO size is determined to
24 Dwords.
An audio sampling frequency of f
the PCI from an audio capture DMA channel of 768 kbytes/s (the bit clock rate is 6144 kbit/s). That accounts for
approximately 13 Dwords per regular video line time. To generate audio output signals, a master read DMA control fills
the output FIFO. A Dword buffer is loaded from FIFO under control of the time slot list. The parallel-to-serial converter
takes a byte as programmed in the time slot list from one of the 8 buffer places; 4 in the Dword buffer and 4 in the
feedback buffer. The serial output is directed to one of the accessible SD pins. Positive and negative clock edge data
transmission is supported by optional BCLK inversion.
Each record in the time slot list describes, how the bytes appearing on the port, are mapped to the Dword wide DMA
channels, respectively to the feedback or input buffers. A time slot list record consists of 4 bytes. As up to 32 time slots
are supported, the time slot list is comprised of 16 Dwords of programming for each audio interface circuit A1 or A2 which
can be linked together.
2004 Aug 25
handbook, full pagewidth
144H
148H
OFFSET
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
FB_BUFFER1
FB_BUFFER2
NAME
FIFO1
4 3 2 1 0
IN
31 to 0
31 to 0
WS4 WS3 WS2 WS1 WS0
s
DATAFLOW CONTROL
WS
= 48 kHz and n = 16 time slots in a super frame results in a maximum data load for
BIT
FIFO1
OUT
Fig.40 Audio data path components.
A1
RW
RW
4 3 2 1 0
TYPE
SD
TSL1
A1
I/O CONTROL
feeds back audio data or stores status/control informations
feeds back audio data or stores status/control informations
109
SD4
TSL2
4 3 2 1 0
A2
DATAFLOW CONTROL
WS
SD3
SD2
A2
FIFO2
IN
SD1
4 3 2 1 0
DESCRIPTION
SD
SD0
FIFO2
OUT
MGG282
Product specification
SAA7146A