74AUP1G17GW,125 NXP Semiconductors, 74AUP1G17GW,125 Datasheet - Page 3

IC BUFF SCHMT TRG LOW PWR 5TSSOP

74AUP1G17GW,125

Manufacturer Part Number
74AUP1G17GW,125
Description
IC BUFF SCHMT TRG LOW PWR 5TSSOP
Manufacturer
NXP Semiconductors
Series
74AUPr
Datasheet

Specifications of 74AUP1G17GW,125

Package / Case
SC-70-5, SC-88A, SOT-323-5, SOT-353, 5-TSSOP
Logic Type
Schmitt Trigger - Buffer, Driver
Number Of Elements
1
Number Of Bits Per Element
1
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
AUP
Number Of Channels Per Chip
1
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 4 mA
Input Bias Current (max)
0.5 uA
Low Level Output Current
4 mA
Maximum Power Dissipation
250 mW
Minimum Operating Temperature
- 40 C
Output Current
20 mA
Output Voltage
4.6 V
Propagation Delay Time
19 ns @ 1.1 V to 1.3 V or 11.2 ns @ 1.4 V to 1.6 V or 9.2 ns @ 1.65 V to 1.95 V or 7 ns @ 2.3 V to 2.7 V or 6.2 ns @ 3 V to 3.6 V
Number Of Lines (input / Output)
1 / 1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2561-2
935279024125
NXP Semiconductors
6. Pinning information
Table 3.
7. Functional description
Table 4.
[1]
74AUP1G17
Product data sheet
Symbol
n.c.
A
GND
Y
n.c.
V
Input
A
L
H
Fig 4.
CC
H = HIGH voltage level; L = LOW voltage level.
GND
n.c.
A
Pin configuration
SOT353-1
Pin description
Function table
1
2
3
74AUP1G17
6.1 Pinning
6.2 Pin description
001aaf170
Pin
TSSOP5
1
2
3
4
-
5
[1]
5
4
V
Y
CC
All information provided in this document is subject to legal disclaimers.
Fig 5.
XSON6
1
2
3
4
5
6
GND
n.c.
Rev. 4 — 15 July 2010
Pin configuration SOT886
A
Transparent top view
74AUP1G17
1
2
3
Output
Y
L
H
Description
not connected
data input
ground (0 V)
data output
not connected
supply voltage
001aaf171
6
5
4
V
n.c.
Y
CC
Fig 6.
GND
Low-power Schmitt trigger
n.c.
Pin configuration SOT891,
SOT1115 and SOT1202
A
Transparent top view
74AUP1G17
74AUP1G17
1
2
3
© NXP B.V. 2010. All rights reserved.
001aaf172
6
5
4
V
n.c.
Y
CC
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