TMPM361F10FG Toshiba, TMPM361F10FG Datasheet - Page 494
TMPM361F10FG
Manufacturer Part Number
TMPM361F10FG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM361F10FG.pdf
(702 pages)
Specifications of TMPM361F10FG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
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Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
100
Package
LQFP(14Ã?14)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
3
Uart/sio (ch)
5
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
8
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
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15.4
Operations
(3)
(4)
(5)
Data sampring timing that specification recommends
by the unit of 1/fs from the minimum value (67/fs, approx. 2.045ms) or the maximum value (90/fs ap-
prox. 2.747ms).
start bit. The received data is discarded.
of 2/fs.
not as an ACK response to the data block when destination address corresponds with the address
set in the logical address register.
CACKDIS>.
(ACK bit: logical "0"). "No" indicates that CEC does not output "0" as a response to the ACK sig-
nal from a transmission device (ACK bit: logical "1").
0 ms
Configure CECRCR1<CECMIN> and <CECMAX> bits to detect a cycle error.
A cycle error can be detected from each sampling clock cycle between the ranges −4/fs to +3/fs
Detecting an error during data reception causes an error interrupt, and CEC waits for the next
Configure the CECRCR1 <CECDAT> bit for the point of determining the data as "0" or "1".
Base time is 34/fs (approx.1.038ms) from the start point and also configurable ±6/fs by the unit
Configuring the CECRCR1 <CECACKDIS> bit enables you to specify if logical "0" is sent or
Logical "0" issent to the header block as an ACK response regardless of the bit setting of <CE-
The following lists the ACK responses.
"Yes" indicates that CEC outputs "0" as a response to the ACK signal from a transmission device
Cycle error
Point of Determining Data
ACK Response
0.6 ms
0.85 ms
Recommended period
(approx.1.038ms)
for data sampling
for data sampling
Reference point
Page 470
<CECDAT>
34/fs ± 6/fs
1.05 ms
1.25 ms
1.5 ms
TMPM361F10FG
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